Description of PhD positions, funded and associated projects.

PhD Positions

The newly established Graduate School “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR) at the University of Stuttgart in cooperation with ADVANTEST invites applications for full-time PhD positions (research assistant) for 3 years with a possibility for extension, 100% TV-L E13 to begin as soon as possible in 2019.

We provide an excellent research environment with the GS-IMTR, the cooperation with ADVANTEST, and within the respective institutes.

In the following, you can find a list of the first PhD positions to be installed:


Prof. Dr. Jens Anders
Institut für Intelligente Sensorik und
Theoretische Elektrotechnik

Pfaffenwaldring 47

D-70569 Stuttgart

Prof. Dr. Ilia Polian
Institut für Technische Informatik
Abt. Hardwareorientierte Informatik

Pfaffenwaldring 47

D-70569 Stuttgart

Co-supervisor: Dr. Matthias Sauer, Advantest

Test quality, defined as the absence of test escapes (defective circuits that had passed post-manufacturing test), is the ultimate target of testing. Customers apply system-level test (SLT) to circuits that already have been tested post-fabrication and reportedly identify test escapes. The objective of this project is to understand the nature of such hard-to-detect failures. Establishing a better understanding of SLT and making it more effective and efficient could drastically improve the economy of circuit design and manufacturing.

A number of theories exist for the type of failures that cause SLT-unique fails that are missed by post-manufacturing tests:

  1. Complex defect mechanisms with subtle parametric or intermittent manifestations that are not adequately covered by standard fault models. The test coverage of such defects can be improved by the use of more advanced defect-oriented models.
  2. Systematic ATPG coverage holes: Insufficient coverage of structures such as clock domain boundaries, asynchronous or analog interfaces, clock distribution networks and other sources of unknown values. Standard automatic test pattern generation (ATPG) tools tend to classify faults in such structures as “untestable” even though they can manifest themselves during normal operation of the device.
  3. Marginal defects exposed only during system-level interactions: Subtle defects, in particular related to timing, in “uncore logic” of complex multicore systems on chip (SoCs), i.e., logic that is part of the SoC but does not belong to a core.

The specific objectives of the project are as follows:

  • To establish a theoretical and systematic understanding of SLT-unique fails, identifying specific mechanisms leading to such fails and their manifestation conditions (e.g., hot-spots).
  • To create an experimentation environment where SLT-unique fails can be reproduced and practically investigated.
  • To explore solutions that prevent or address SLT-unique fails. These can include guidelines for “clean” circuit designs that do not give rise to coverage holes (e.g., use of well-defined asynchronous protocols for clock domain crossings); design for testability (DFT) methods that address specific weaknesses known to the designer or DFT engineer; extended ATPG methods that can detect defects missed by regular ATPG, or methods to create effective and efficient SLTs that specifically target SLT-unique failure mechanisms.
Task 2: Evaluation and Experimentation


The project is structured into three tasks according to the three above-mentioned scientific objectives. The more theoretical Tasks 1 and 3 deal with SLT-unique fails and solutions to counteract them, respectively. Task 2 will establish a complete evaluation and experimentation flow that can be used for practical demonstration of SLT-unique fails and studies of applicable solutions. Figure 1 summarizes the planned project structure and the interaction of its theoretical (red) and practical (blue) parts. An SLT evaluation platform will be created and SLT-unique fail conditions from Task 1 will be incorporated into this platform. Based on the outcome of experiments , solutions for the SLT-unique fails from Task 3 (e.g., addition of special DFT logic) will be incorporated into the SLT evaluation platform , thus closing the loop.

Project lead

Thomas Ertl, Steffen Koch, Daniel Weiskopf

We are looking for

A motivated applicant with a very good master’s degree in computer science or related disciplines. The candidate should have strong programming skills. A background in visualization, data analysis, machine learning, or a combination thereof is beneficial.

Project summary

This project aims to tackle challenges occurring in post-silicon validation with visual analytics methods. Visual analytics helps users analyze complex problems iteratively and supports the steering of complex analysis processes. It therefore constitutes a valid approach to address some of the difficult problems occurring in post-silicon analysis. These include the comparison of high-dimensional test parameters and output parameter spaces, the sparseness of errors and resulting difficulties to develop hypotheses on problem causes, as well as the validation of hypotheses including the generation of new test parameters if necessary.

The project’s goal is to develop new visual analytics approaches in close cooperation with chip testing experts, and to organize successful visual solutions into coherent interactive analysis workflows.

The research in this project is planned to lead to a doctoral thesis in computer science, focusing on visualization and visual analytics. To support successful research for the thesis, we provide an excellent research environment with the Graduate School “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR), the cooperation with ADVANTEST, as well as with the Institute for Visualization and Interactive Systems (VIS) and the Visualization Research Center (VISUS) at the University of Stuttgart.

Project lead

Dirk Pflüger

What we are looking for:
  • MSc graduate in computer science, mathematics, data science, electrical engineering or a related field
  • Strong mathematical skills
  • Programming experience (preferably Python and/or C++)
  • Knowledge of dimensionality reduction, parameter identification, high-dimensional approximation, or inverse problems are an asset

The generation of meaningful test sets in semiconductor testing plays an important role to fast and cost-efficient testing. The goal of this project is to improve beyond pure stochastic sampling which provides valid though very large test sets. We will therefore develop a (semi-)automatic methodological framework for the self-learning generation of meaningful test sets and their analysis.
The project strives to provide guided, intelligent sampling of the parameter space of the test function based on the analysis of the currently gathered data. The aim is to add test cases to best increase the information gain about the exploration of the input space, combining, for example, methods from statistics, big data, and higher-dimensional approximation.

Project lead

Ralf Küsters

What we are looking for:
  • MSc graduate in computer science, mathematics, cyber security, or a related field
  • Strong mathematical skills
  • Knowledge of cryptography, in particular, multi-party computation, zero-knowledge proofs, and/or fully homomorphic encryption is an asset

Semiconductor testing plays an important role in the semiconductor manufacturing process. The tests not only ensure the quality of individual chips, but the data obtained during the tests is used to improve the manufacturing process itself. Often manufacturers use third-party services to perform the tests and evaluate the test data, as this requires specialized expertise. Since the test data and the models and methods to evaluate the data, such as machine learning models, are typically highly sensitive trade secrets, on the one hand, manufacturers are reluctant to share their test data with third-party evaluation services, and on the other hand, the services do not want to reveal their evaluation models and methods.

The idea of the project is to use, further develop, and adapt secure cryptographic protocols, to protect the digital assets in a globalized and distributed semiconductor manufacturing flow.

The open positions are integrated into the GS-IMTR which provide

  • A structured, quality-assured and interdisciplinary education programme;
  • Subject-specific lectures and seminars for soft skills and interpersonal skills;
  • International networking during a stay at research institutes abroad.

Applicants should hold a master’s or equivalent degree in electrical engineering, computer science, information technology, mathematics, physics, or a related discipline with above-average results. They are expected to show a high level of proficiency in both spoken and written English.

Please send your application (cover letter, academic CV, letter of motivation indicating your favorite project(s), degree certificates and transcripts of records from Bachelor/Master, names of potential academic referees) either by post to Prof. Dr. Dirk Pflüger, Institute for Parallel and Distributed Systems, Universitätsstr. 38, 70569 Stuttgart, Germany, or electronically in a single PDF file (up to 10 MB) to to arrive no later than September 5, 2019. As there will be a second call for further doctoral positions in the near future, later submissions might be taken into consideration.

The University of Stuttgart is an equal opportunities employer. Applications from women are especially encouraged. Severely challenged persons will be given preference in case of equal professional qualifications.

Dieses Bild zeigt Pflüger
Prof. Dr. rer. nat.

Dirk Pflüger

Institute for Parallel and Distributed Systems (IPVS)

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