Events

Information about upcoming, related and past GS-IMTR events.

2022

Five PhD students of GS-IMTR attended the 34. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ 2022) in Bremerhaven in person during 27.02-01.03.2022. Four of them (Florian, Nourhan, Peter, Yiwen) had  either a poster or an oral presentation and Denis just attended due to interest. There were many exciting discussions after the poster and presentation. Since it was the first in-person workshop after a long Corona break, it was also an exciting event for all attendees. Some personal impressions from our PhD students:

Peter Domanski: My feedback for TuZ'22 is that there seems to be a large interest in machine learning approaches to testing problems. Experts seem to be well aware of the increasing difficulties in testing modern era semiconductor devices. At the same time, there is a little bit of fear that ML algorithms could replace their jobs. Moreover, I got the impression that in addition they want to understand how ML algorithms are able to improve their jobs.

Nourhan Elhamawy: A very exclusive community for testing with a common goal to make testing more efficient.

Florian Klemme: I enjoyed the TuZ workshop a lot! The familial atmosphere made it easy to get into conversations and connect to other researchers. Despite the small size of the workshop, talks were covering a wide range of test topics - from silicon to automotive and medical applications.

Yiwen Liao: On-site workshop made it possible to have better communication opportunities with experts from other fields. Moreover, I can feel that using artificial intelligence has become a very important direction for test and reliability in the near future. It would be very exciting if there will be more and more discussions from both sides.

Denis Schwachhofer:  TuZ has been a great opportunity to get back into meeting in person. There have been many interesting presentations and posters (the talk from Frank Sill Torres about resilience for example) but also opportunities for discussion and the boat tour has also of course been a treat.

Five members of the GS-IMTR attended the conference "Design, Automation and Test in Europe 2022" (DATE'22) from March 14 to March 23. Due to Covid'19, the conference was purely virtual. DATE'22 gave us the opportunity to present the overal picture of the GS-IMTR to the broader scientific community.

In the Multi-Partner-Projects Session, Paul Genssler presented the GS-IMTR as a whole. Both in a pre-recorded presentation and a short live teaser including questions and answers.

Dirk Pflüger was panelist in the panel "The Good, the Bad and the Trendy of Multi-Partner Research Projects in Europe", discussing funding schemes and best practice examples for multi-partner projects. Due to its funding by Advantest, the GS-IMTR served as an exemplary role-model for joint university-industry research. Further participants in the panel: Lorena Anghel, Anton Chichkov, Yves Gigase, Christoph Grimm, Said Hamdioui, Peter Hofmann, Maksim Jenihhin, and Daniel Watzenig.

Natalia Lylina presented her paper on "Robust reconfigurable scan networks" and took part in the PhD Forum.

With Hussam Amrouch and Ilia Polian (Session Chair and DEC Member) two more representatives of the GS-IMTR took an active role.

Social event of TSS
Social event of TSS
Short summary for TSS/ETS/Workshop

3 Professors and 9 PhD students from GS-IMTR attended the 27th IEEE European Test Symposium (ETS) from May 23th to 27th 2022 in Barcelona, Spain. This year, 20 scientific papers have been accepted for oral presentations and 18 papers have been presented in posters at ETS. Moreover, 4 invited keynote talks, 4 special sessions, 3 embedded tutorials, 2 panels, 3 vendor sessions, one PhD forum were available at ETS’22. The topics were diverse and exciting, including but not limited to RF 5G test, automobile SoC functional safety, AI-assisted yield learning, IJTAG test standard and many more. Paria Najafi of GS-IMTR presented her work “On Extracting Reliability Information from Speed Binning” at the session for “Functional Safety”. Prof. Dirk Pflüger, Prof. Krishnendu Chakrabarty, Prof. Hussam Amrouch and Matthias Sauer presented their views on machine learning for test, diagnosis, post-silicon validation and yield optimization in a special session.

Co-organized with ETS’22, the fringe workshop Intelligent Methods for Test and Reliability (1st IMTR Workshop) was also attractive, including 3 keynote talks, one panel session and 9 scientific paper presentations. 7 PhD students from GS-IMTR presented their recent work at the workshop and there were fruitful discussions after each presentation.

As usual, the Test Spring School (TSS) was offered before ETS’22 from May 20th to May 23th, 2022. The main topic of TSS’22 is “AI for IC dependability and dependability of AI ICs”, covered by 6 lectures from both industry and academia. Along with the lectures, there were two social events: visiting Sagrada Família and Park Güell. Overall, the whole event (TSS/ETS/Workshop) was exciting and inspiring.

Here is some feedback from one of our PhD students Natascha Lylina: Overall, visiting ETS and TTS is a motivating experience, especially after 2 years of Pandemic. It has been very encouraging to meet new people, as well as to meet old friends, and to see how they enhanced their research throughout those 2 years. Most of the talks at TSS were interesting. The organization was very good. We have met many interesting researchers from the whole Europe. The only minor point is that it might be easier to follow if the students would get the transcript of the lectures before the TSS started. Lecture of Prof. Amrouch was wonderful -- it would have been so nice, if he would find some time at least every half a year to present something to the GS-IMTR students! This would help to fill the gap between the pure ML-students and the test-students. The talks at ETS mostly have been done in a high quality and would help us to enhance our own research. However, the hybrid part of the event has not worked perfectly, since dynamic rescheduling on-site has not been properly and in-time transmitted to online participants. AI and ML for test is a clear trend at ETS. However, at one of the talks it was addressed that the application areas where it is relevant to use ML for enhancing test must be selected more thoroughly, and the choice of ML for solving some test problems must be better justified. At one of the talks at TSS, mostly US and few European groups have been named as the principal investigators for applying ML to test. I believe that the next milestone for GS-IMTR could be that the GS-IMTR becomes even more well-known in connection to (ML-based test), such that each further speaker includes our group to this list by default. To do this, more publications at test conferences/journals can be achieved. Thanks to GS-IMTR and Advantest for giving us such a nice opportunity to visit a leading test conference, meet new people and listen to nice and motivating talks! We really appreciate this!

Attendees:
Professors from GS-IMTR: Prof. Dirk Pflüger, Prof. Hussam Amrouch, Prof. Ilia Polian
PhD students from GS-IMTR: Andres Lalama, Denis Schwachhofer, Hanieh Jafarzadeh, Natascha Lylina, Nourhan Elhamawy, Paria Najafi, Paul Genssler, Sebastian Hasler, Yiwen Liao.
Advantest: Dr. Mattias Sauer, Georg Karich, Sarah Rottacker

Group photo at ETS
Group photo at ETS
Short summary for TSS/ETS/Workshop

3 Professors and 9 PhD students from GS-IMTR attended the 27th IEEE European Test Symposium (ETS) from May 23th to 27th 2022 in Barcelona, Spain. This year, 20 scientific papers have been accepted for oral presentations and 18 papers have been presented in posters at ETS. Moreover, 4 invited keynote talks, 4 special sessions, 3 embedded tutorials, 2 panels, 3 vendor sessions, one PhD forum were available at ETS’22. The topics were diverse and exciting, including but not limited to RF 5G test, automobile SoC functional safety, AI-assisted yield learning, IJTAG test standard and many more. Paria Najafi of GS-IMTR presented her work “On Extracting Reliability Information from Speed Binning” at the session for “Functional Safety”. Prof. Dirk Pflüger, Prof. Krishnendu Chakrabarty, Prof. Hussam Amrouch and Matthias Sauer presented their views on machine learning for test, diagnosis, post-silicon validation and yield optimization in a special session.

Co-organized with ETS’22, the fringe workshop Intelligent Methods for Test and Reliability (1st IMTR Workshop) was also attractive, including 3 keynote talks, one panel session and 9 scientific paper presentations. 7 PhD students from GS-IMTR presented their recent work at the workshop and there were fruitful discussions after each presentation.

As usual, the Test Spring School (TSS) was offered before ETS’22 from May 20th to May 23th, 2022. The main topic of TSS’22 is “AI for IC dependability and dependability of AI ICs”, covered by 6 lectures from both industry and academia. Along with the lectures, there were two social events: visiting Sagrada Família and Park Güell. Overall, the whole event (TSS/ETS/Workshop) was exciting and inspiring.

Here is some feedback from one of our PhD students Natascha Lylina: Overall, visiting ETS and TTS is a motivating experience, especially after 2 years of Pandemic. It has been very encouraging to meet new people, as well as to meet old friends, and to see how they enhanced their research throughout those 2 years. Most of the talks at TSS were interesting. The organization was very good. We have met many interesting researchers from the whole Europe. The only minor point is that it might be easier to follow if the students would get the transcript of the lectures before the TSS started. Lecture of Prof. Amrouch was wonderful -- it would have been so nice, if he would find some time at least every half a year to present something to the GS-IMTR students! This would help to fill the gap between the pure ML-students and the test-students. The talks at ETS mostly have been done in a high quality and would help us to enhance our own research. However, the hybrid part of the event has not worked perfectly, since dynamic rescheduling on-site has not been properly and in-time transmitted to online participants. AI and ML for test is a clear trend at ETS. However, at one of the talks it was addressed that the application areas where it is relevant to use ML for enhancing test must be selected more thoroughly, and the choice of ML for solving some test problems must be better justified. At one of the talks at TSS, mostly US and few European groups have been named as the principal investigators for applying ML to test. I believe that the next milestone for GS-IMTR could be that the GS-IMTR becomes even more well-known in connection to (ML-based test), such that each further speaker includes our group to this list by default. To do this, more publications at test conferences/journals can be achieved. Thanks to GS-IMTR and Advantest for giving us such a nice opportunity to visit a leading test conference, meet new people and listen to nice and motivating talks! We really appreciate this!

Attendees:
Professors from GS-IMTR: Prof. Dirk Pflüger, Prof. Hussam Amrouch, Prof. Ilia Polian
PhD students from GS-IMTR: Andres Lalama, Denis Schwachhofer, Hanieh Jafarzadeh, Natascha Lylina, Nourhan Elhamawy, Paria Najafi, Paul Genssler, Sebastian Hasler, Yiwen Liao.
Advantest: Dr. Mattias Sauer, Georg Karich, Sarah Rottacker

Prof. Pflüger presented cartoons for GS-IMTR
Prof. Pflüger presented cartoons for GS-IMTR
Short summary for Workshop

Co-organized with ETS’22, the fringe workshop Intelligent Methods for Test and Reliability (1st IMTR Workshop) was also attractive, including 3 keynote talks, one panel session and 9 scientific paper presentations. 7 PhD students from GS-IMTR presented their recent work at the workshop and there were fruitful discussions after each presentation.

Talk in the International Speaker Series, Prof. Dr. Jinjun Xiong

On Monday July 25 2022, Prof. Jinjun Xiong gave a talk in the GS-IMTR's International Speaker Series. His talk was titled "From Statistical Circuit Analysis and Optimization to a Novel Deep Neural Network Design".

Abstract: The impressive results achieved by deep neural networks (DNNs) in various tasks, computer vision in particular, such as image recognition, object detection, and image segmentation, have sparked the recent surging interests in artificial intelligence (AI) from both the industry and the academia alike. The wide adoption of DNN models in real-time applications has, however, brought up a need for more effective training of an easily parallelizable DNN model for low latency and high throughput. This is particularly challenging because of DNN's deep structures. To address this challenge, we observe that most of existing DNN models operate on deterministic numbers and process one single frame of image at a time, and may not fully utilize the temporal and contextual correlation typically present in multiple channels of the same image or adjacent frames from a video. Seemingly quite unrelated, the EDA community has developed many solid foundations in statistical circuit timing analysis and optimization in the past couple of decades to combat the process uncertainties in designing VLSI circuits and devices. By bridging the domain knowledge gaps from the two seemingly different communities, we propose a novel statistical distribution-based DNN model that extends existing DNN architectures but operates directly on correlated distributions rather than deterministic numbers. This new perspective of training DNN has resulted in surprising effects on achieving not only improved learning accuracy, but also reduced latency and increased high throughputs. Our experimental results on various tasks, including 3D Cardiac Cine MRI segmentation, showed a great potential of this new type of statistical distribution-based DNN model, which warrants further investigation. This talk further illustrates the importance of interdisciplinary collaboration in novel scientific discovery.

Bio: Dr. Jinjun Xiong is currently Empire Innovation Professor with the Department of Computer Science and Engineering at University at Buffalo (UB). Prior to that, he was a Senior Researcher and Program Director for AI and Hybrid Clouds Systems at the IBM Thomas J. Watson Research Center. He co-founded and co-directed the IBM-Illinois Center for Cognitive Computing Systems Research from 2016-2021, the success of which led to the $200M 10-year investment to establish the IBM-Illinois Discovery Accelerator Institute in 2021. His research interests are on across-stack AI systems research, which include AI applications, algorithms, tooling, and computer architectures. Many of his research results have been adopted in IBM’s products and tools. He published more than 150 peer-reviewed papers in top AI conferences and systems conferences. His publication won 8 Best Paper Awards and 8 Nominations for Best Paper Awards. He also won top awards from various international competitions, including the recent champion for the IEEE GraphChallenge on accelerating sparse neural networks, and champions for the DAC'19 Systems Design Contest on designing an object detection neural network for edge FPGA and GPU devices.

Graph Neural Networks for Hardware Design, Security and Reliability

On Monday August 1 2022, Dr. Lilas Alrahis gave a talk about her research on Graph Neural Networks for hardware design, security and reliability.

Abstract: Graph Neural Networks (GNNs) successfully facilitate learning on graph-structured data, such as social networks, recommendation systems, and protein-protein interactions. Since electronic circuits can be represented naturally as graphs, GNNs provide great potential to advance Machine Learning (ML)-based methods for all aspects of electronic system design and Computer-Aided Design (CAD). This talk provides an overview of how GNNs get designed and employed to learn the properties of circuits. Taking hardware security and circuit reliability assessments as target applications, this talk first illustrates how GNNs aid in analyzing flattened/unstructured gate-level netlists, then demonstrates how to employ GNNs to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit.

Bio: Lilas Alrahis received the M.Sc. degree and the Ph.D. degree in Electrical and Computer Engineering from Khalifa University, UAE, in 2016 and 2021, respectively. She is currently a Postdoctoral Associate with the Design for Excellence Lab, headed by Prof. Ozgur Sinanoglu, in the Division of Engineering, at the New York University Abu Dhabi (NYUAD), UAE. Her current research interests include Hardware Security, Design-for-Trust, Logic Locking, Applied Machine Learning, and Digital Logic Design. Dr. Alrahis is currently serving as Associate Editor of the Integration, the VLSI Journal. She is also a frequent reviewer for top journals including IEEE Transactions on Information Forensics and Security, IEEE Access, and IEEE Embedded Systems Letters. She was a program committee member of the Euromicro Conference on Digital System Design (DSD2021 and DSD2022). Dr. Alrahis won the MWSCAS Myril B. Reed Best Paper Award in 2016 and the Best Paper Award at the Applied Research Competition held in conjunction with Cyber Security Awareness Week in 2019 and 2021.

Guest talk on "Error resilience and security of DNNs", Prof. Abhijit Chatterjee

Guest talk on "Error resilience and security of DNNs" by Abhijit Chatterjee (Georgia Tech, Guest Professor in GS-IMTR)

The Graduate School Intelligent Methods for Test and Reliability is proud to announce the first visitor in its Guest Professor program: Prof. Abhijit Chatterjee of Georgia Tech, Atlanta, USA. The topic of this talk "Error resilience and security of DNNs" can be of interest for many both within and beyond GS-IMTR!

Abstract: The reliability and security of deep neural networks (DNNs) is of great concern due to their widespread use in data-intensive applications. Ensuring the same is made difficult due to the typically large numbers of neurons in such systems and the complex relationship between errors in computation and their effects on network performance accuracy. In this talk, we study the problem of designing error-resilient DNNs where errors can stem from: (a) soft errors in computation of matrix-vector multiplications and neuron activations, (b) malicious trojan and adversarial security attacks and (c) effects of manufacturing process variations on analog crossbar arrays that can affect DNN accuracy. The core principle of error detection relies on internal state space encodings of the DNN input, hidden and output layers. This makes use of prior results in the domain of algorithmic checksums widely used for error detection in linear signal processing application. A key contribution is in adapting such checking techniques to the inherent nonlinearity of neuron computations with minimal impact on error detection coverage. Once errors are detected, they are corrected using probabilistic methods due the difficulties involved in exact diagnosis of errors in such complex systems. The technique is scalable across soft errors as well as a variety of security attacks. The effects of manufacturing process variations are handled through the use of compact tests from which DNN performance can be predicted using nonlinear regressors. Experimental results on a variety of test cases are presented to demonstrate the viability of the proposed techniques.

BIO: Abhijit Chatterjee is a Professor in the School of Electrical and Computer Engineering at Georgia Tech and a Fellow of the IEEE. He received his Ph.D in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. Dr. Chatterjee received the NSF Research Initiation Award in 1993 and the NSF CAREER Award in 1995. He has received seven Best Paper Awards and three Best Paper Award nominations. His work on self-healing chips was featured as one of General Electric’s key technical achievements in 1992 and was cited by the Wall Street Journal. In 1995, he was named a Collaborating Partner in NASA’s New Millennium project. In 1996, he received the Outstanding Faculty for Research Award from the Georgia Tech Packaging Research Center, and in 2000, he received the Outstanding Faculty for Technology Transfer Award, also given by the Packaging Research Center. In 2007, his group received the Margarida Jacome Award for work on VIZOR: Virtually Zero Margin Adaptive RF from the Berkeley Gigascale Research Center (GSRC). Dr. Chatterjee has authored over 450 papers in refereed journals and meetings and has 22 patents. He is a co-founder of Ardext Technologies Inc., a mixed-signal test solutions company and served as chairman and chief scientist from 2000-2002. His research interests include error-resilient signal processing and control systems, mixed-signal/RF/multi-GHz design and test and adaptive real-time systems.

The doctoral researcher of the GS-IMTR got together from August 15 to August 18 for the first retreat. Their background and research foci were diverse and spread across the area of computer science and electrical engineering. At the Tagungshaus Schönenberg in Ellwangen, they used the first multi-day in-person meeting to exchange their knowledge of their field and presented their latest research work. They listed and demonstrated their technical skills to their peers to better understand the whole semiconductor lifecycle and associated data processing. As a result, new collaborations between the doctoral students were started and existing ones extended.

Talk by Dr. Knechtel

2.5D and 3D Integration - Another Dimension Toward Secure Hardware

Abstract: As with most aspects of electronic systems, hardware security has traditionally evolved around CMOS technology and traditional integration and packaging options. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of traditional CMOS approaches, unique opportunities do also arise to advance the notion of hardware security. In this talk, I will first introduce the different concepts of hardware security in general and I will review 2.5D and 3D integration as emerging technology option. In the main part of the talk, I will then discuss the application of 2.5D and 3D integration to advance the different concepts for hardware security and I will also outline related and novel challenges.

Bio: Johann Knechtel is a Research Scientist with the New York University Abu Dhabi, United Arab Emirates. He received the M.Sc. degree in Information Systems Engineering (Dipl. Ing.) and the Ph.D. degree in Computer Engineering (Dr. Ing., summa cum laude) from TU Dresden, Germany, in 2010 and 2014, respectively. His research interests cover VLSI physical design automation, with particular focus on emerging technologies and hardware security. He was a Postdoctoral Researcher with the Masdar Institute of Science and Technology, Abu Dhabi, from 2015 2016. From 2010 to 2014, he was a Ph.D. Scholar with the DFG Graduate School on “Nano and Biotechnologies for Packaging of Electronic Systems” at TU Dresden. In 2012, he was a Research Assistant with the Chinese University of Hong Kong, Hong Kong. In 2010, he was a Visiting Research Student with the University of Michigan at Ann Arbor, MI, USA.

Talk in the International Speaker Series, Prof. X. Sharon Hu

On Monday September 05 2022, Prof. Xiaobo Sharon Hu gave a talk in the GS-IMTR's International Speaker Series about her research on cross the technology stack, from device to application, for in-memory computing.

Abstract: Data transfer between processors and memory is a major bottleneck in improving application performance on traditional computing hardware. This is particularly true for data intensive workloads such as many machine learning, bioinformatics and security applications. In-memory computing (IMC), where significant amount of data processing is performed directly in memory, can be an effective alternative to address this bottleneck. However, due to the myriad of design options for an IMC based solution, harnessing the benefits of the IMC paradigm requires cross-layer efforts spanning from devices and circuits to architectures and systems.

This talk will showcase several representative cross-layer IMC-based design efforts. In particular, the talk will highlight how ferroelectric FETs, an emerging non-volatile device technology, can be exploited to implement various IMC functions (e.g., exact and best match for associative search, configurable look-up tables, etc.), and what are some unique challenges in designing IMC circuits and architectures. IMC solutions for several popular machine learning and other applications will be analyzed end-to-end to reveal the benefits contributed by each design layer, which can serve as guides for future research efforts.

Bio: X. Sharon Hu is a professor in the department of Computer Science and Engineering at the University of Notre Dame, USA. Her research interests include low-power system design, circuit and architecture design with emerging technologies, real-time embedded systems and hardware-software co-design. She has published more than 400 papers in these areas. Some of her recognitions include the Best Paper Award from the Design Automation Conference and  the International Symposium on Low Power Electronics and Design, and NSF Career award. She has participated in several large industry and government sponsored center-level projects and was a theme lead in an NSF/SRC E2CDA project. She served as the General Chair and TPC Chair of Design Automation Conference, Real-Time Systems Symposium, etc. She is the Editor-in-Chief of ACM Transactions on Design Automation of Electronic Systems, and has also served as Associate Editor for a number of ACM and IEEE journals. X. Sharon Hu is a Fellow of the ACM and a Fellow of the IEEE.

This image shows Ilia Polian

Ilia Polian

Prof. Dr. rer. nat. habil.

Institute of Computer Architecture and Computer Engineering

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