Publications

Abstract

System-Level Test (SLT) is crucial for evaluating integrated circuits as it can detect defects that traditional testing misses. Nowadays, test engineers manually compose test suites using off-the-shelf software. This process, however, is an arduous task and offers only limited control over non-functional properties. As such, it is of interest to research methods to automatically generate SLT programs. This work compares three methods for test program generation for SLT, specifically targeting non-functional properties, namely fuzzing, genetic programming, and Large Language Models (LLMs). For this comparison, we will let these methods run for 24 hours to generate as many snippets as possible to maximize the power consumption of a RISC-V-based processor.

Abstract

We construct a pseudorandom correlation function (PCF) for oblivious linear evaluation (OLE) from sparse LPN over any finite field. The programmability property of our PCF implies a PCF for any multiparty degree-two correlation, e.g., Beaver triples. Our PCF is the first PCF for degree-two correlations from a well-established cryptographic assumption, apart from (inefficient) generic PCFs based on homomorphic secret sharing or fully homomorphic encryption. Our PCF outperforms the previously fastest PCF for Beaver triples (Boyle et al., Crypto 2022) by 3.2-28x. We build on the recent pseudorandom correlation generator (PCG) by Miao et al. (Asiacrypt 2025) and extend it to a PCF using a recursive approach similar to Braun et al. (Asiacrypt 2025). Moreover, we extend these techniques to support authenticated degree-two correlations in the important two-party case.

Abstract

State-of-the-art actively secure multi-party computation protocols, like SPDZ (Damgård et al., CRYPTO 2012), use correlated randomness, like Beaver triples, to achieve a highly efficient online phase. For a long time, the generation of the correlated randomness in the offline phase relied on classical cryptographic primitives, like somewhat homomorphic encryption or oblivious transfer, that required significant communication. More recently, Boyle et al. (FOCS 2020) defined a new primitive called pseudorandom correlation functions (PCFs) to generate correlated randomness non-interactively. PCFs set up keys for each party in an initial interactive phase, which can then be used by the parties to generate a large number of shares of the correlated randomness without further communication. In the random oracle model (ROM), two-party PCFs can be generically constructed based on evaluating a weak pseudorandom function (WPRF) using a powerful-enough homomorphic secret sharing scheme. However, the concrete efficiency of instantiations of this approach has not been analyzed so far. There are also some works that construct PCFs based on other approaches, but they cannot be used for correlations of degree >= 2 (e.g., Beaver triples) over large rings/fields (such as those used in SPDZ). In this paper, we improve the complexity and concrete efficiency of PCFs over large rings/fields by presenting a new generic PCF based on the hardness of the ring-learning with rounding (Ring-LWR) problem and FHE. We only share BFV keys in the initial interactive phase. The two parties then use the random oracle to locally sample BFV (pseudo-)ciphertexts encrypting pseudorandom plaintexts. We use a new bootstrapping algorithm for these (pseudo-)ciphertexts that reduces initially saturated noise to a level where the parties can use the homomorphic properties of the BFV scheme to correlate the encrypted randomness locally. Both parties can then produce, without further interaction, shares of the correlated randomness with their secret key share. Our new PCF works with any form of correlated randomness that can be expressed as an arithmetic circuit over a base ring Z_t or field F_p^d, e.g., Beaver or matrix triples.

Abstract

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since timing variations can invalidate the effectiveness of such patterns, different circuit instances may show a different fault coverage for the same test pattern set. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings introduced by process and temperature-induced variations. The method overcomes the limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations due to the computational complexity. A statistical learning scheme maximises the coverage of SDFs in circuits following the variation parameters of a calibrated in- dustrial FinFET transistor model. The method combines efficient ATPG for Transition Faults (TFs) with fast timing-aware fault simulation on GPUs. Simulation experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detection for transition faults, while the fault coverage even increases.

Abstract

System-Level Test (SLT) is essential for testing integrated circuits, focusing on functional and non-functional properties of the Device under Test (DUT). Traditionally, test engineers manually create tests with commercial software to simulate the DUT's end-user environment. This process is both time-consuming and offers limited control over non-functional properties. This paper proposes Large Language Models (LLMs) enhanced by Structural Chain of Thought (SCoT) prompting, a temperature schedule, and a pool of previously generated snippets to generate high-quality code snippets for SLT. We repeatedly query the LLM for a better snippet using previously generated snippets as examples, thus creating an iterative optimization loop. This approach can automatically generate snippets for SLT that target specific non-functional properties, reducing time and effort. Our findings show that this approach improves the quality of the generated snippets compared to unstructured prompts containing only a task description.

Abstract

Logic Built-In Self-Test (LBIST) with stored de- terministic patterns is supported by the major CAD vendors and is gaining increasing attention, especially for safety-critical applications such as automotive. It is used for both manufacturing and periodic in-field testing. An unresolved challenge so far stems from the inevitable process. This paper presents the first approach for storage-based BIST addressing delay faults under process variations and multiple voltages. A unified solution for pattern generation, test set compaction and BIST hardware is presented that is compatible with commercial schemes. The solu- tion significantly outperforms traditional N-detect for transition faults in terms of test set size, test application time and fault efficiency.

Abstract

It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into Stuck-at-faults. It is often overlooked that Vmin testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under Vmin is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first test pattern generation algorithm specifically tuned for Vmin testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage.

Abstract

Reliability is one of the key concerns in circuit design. The circuit must be able to tolerate transistor degradation to sustain reliability against timing failure. Whether a transistor is degraded due to noise, aging, or poor manufacturing, a circuit must uphold a timing error-free functionality over its entire projected lifetime. Transistors are hardened (designed stronger than necessary) to tolerate these degradations. However, hardening (e.g., widening the transistors) comes at the cost of additional area and power. Hence, it is necessary to identify and selectively harden specific transistors within a circuit. In this work, transistors that prolong a circuit’s delay when they are degraded are termed “susceptible”, and thus, are to be hardened. Identifying the susceptible transistors within a circuit is a complex task, for example, Monte Carlo circuit simulations require days to identify susceptible transistors in a single circuit. Consequently, current solutions are costly in terms of time and limited in their application. Instead, machine learning (ML) can offer a fast (inference in seconds) and universal (applicable to unseen circuits) alternative. However, traditional ML techniques struggle with inference on topology-based problems, while recent graph neural networks (GNNs) excel in these applications. Therefore, this work presents the first ML to classify susceptible transistors with GNNs. We use GNNs, specifically Graph Attention Networks (GAT), because the topology of the cell strongly affects how each transistor degradation affects performance. For instance, series-connected transistors amplify their impact, while parallel-connected ones can offset each other’s influence. Our GAT-based approach employs a heterogeneous graph in combination with GAT’s attention mechanism to capture the circuit’s topology and its impact on the analysis. Our evaluation demonstrates the capability of our approach to classifying transistors according to their impact within the ASAP7 standard cell library’s standard cells in mere 0.04 s (compared to days of Monte Carlo simulation time) while achieving 80.4% accuracy on unseen circuits.

Abstract

Many of the currently best actively secure Multi-Party Computation (MPC) protocols like SPDZ (Damgård et al., CRYPTO 2012) and improvements thereof use correlated randomness to speed up the time-critical online phase. Although many of these protocols still rely on classical Beaver triples, recent results show that more complex correlations like matrix or convolution triples lead to more efficient evaluations of the corresponding operations, i.e. matrix multiplications or tensor convolutions. In this paper, we address the evaluation of multivariate polynomials with a new form of randomness: polytuples. We use the polytuples to construct a new family of randomized encodings which then allow us to evaluate the given multivariate polynomial. Our approach can be fine-tuned in various ways to the constraints of applications at hand, in terms of round complexity, bandwidth, and tuple size. We show that for many real-world setups, a polytuples-based online phase outperforms state-of-the-art protocols based on Beaver triples.

Abstract

In recent years, actively secure SPDZ-like protocols for dishonest majority, like SPDZ2k, Overdrive2k, and MHz2k, over base rings Z2k have become more and more efficient. In this paper, we present a new actively secure MPC protocol Multipars that outperforms these state-of-the-art protocols over Z2k by more than a factor of 2 in the two-party setup in terms of communication. Multipars is the first actively secure N-party protocol over Z2k that is based on linear homomorphic encryption (LHE) in the offline phase (instead of oblivious transfer or somewhat homomorphic encryption in previous works). The strong performance of Multipars relies on a new adaptive packing for BGV ciphertexts that allows us to reduce the parameter size of the encryption scheme and the overall communication cost. Additionally, we use modulus switching for further size reduction, a new type of enhanced CPA security over Z2k, a truncation protocol for Beaver triples, and a new LHE-based offline protocol without sacrificing over Z2k. We have implemented Multipars and therewith provide the fastest preprocessing phase over Z2k. Our evaluation shows that Multipars offers at least a factor of 8 lower communication costs and up to a factor of 10.2 faster runtime in the WAN setting compared to the currently best available MPC implementation over Z2k.

Abstract

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectivity of such patterns, different circuit instances may show a different fault coverage. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the complexity limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations. A statistical learning scheme maximises the coverage of SDFs in an entire circuit population following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults with fast timing-aware fault simulation on GPUs. Experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detect while the fault coverage even increases compared to both N-detect and timing-aware ATPG

Abstract

The Preconditioned Conjugate Gradient (PCG) method is well-established for solving linear equations systems. Running the PCG method on a hardware accelerator ensures fast and efficient computation. At the same time, each hardware accelerator may be slightly different due to process variability or aging. To handle the variability, a rather pessimistic frequency selection for the whole population of accelerators is often utilized. Increasing the frequency may improve the performance but may also increase the risk of computational errors, affect the convergence of PCG or even corrupt the PCG results. In this paper, we present a method to determine the frequency for each hardware accelerator instance which optimizes the execution time and the energy efficiency of the PCG method. First, a technique is presented to analyze the error resilience of a PCG algorithm to overclocking. Based on the analysis results, we increase the frequency to speed up the convergence while keeping the error rate below the required threshold.

Abstract

Many applications from Artificial Intelligence (AI) and Scientific Computing rely on efficient algorithms for solving large systems of linear equations. The Preconditioned Conjugate Gradient (PCG) algorithm is a promising option and it is a perfect candidate to be executed on specialized hardware accelerators widely used in AI. Hardware accelerators, like other modern devices, are prone to process variations. A conventional approach to handle the variability is to use pessimistic guard�bands for all the devices within the population, which implies that the best and even the average accelerators are slowed down significantly. Since the PCG algorithm is inherently error resilient to some extent, it may also tolerate an error rate increase due to overclocking. On another side, increasing the frequency may increase the total execution time if more arithmetic operations are needed until the convergence. This paper presents a method to ensure efficient computing on each hardware accelerator instance running the PCG algorithm. A cross-layer approach identifies an optimized frequency that minimizes the total time to complete the PCG algorithm. Simple high-level checks ensure the quality of the solution. Experimental results validate the feasibility of the developed approach for large systems of linear equations.

Abstract

The high-volume manufacturing test ensures the production of defect-free devices, which is of utmost importance when dealing with safety-critical systems. Such a high-quality test requires a deliberately designed scan network to provide a time and cost-effective access to many on-chip components, as included in state-of-the-art chip designs. The IEEE 1687 Std. (IJTAG) has been introduced to tackle this challenge by adding programmable components that enables the design of reconfig- urable scan networks. Although these networks reduce the test time by shortening the scan chains’ lengths, the reconfiguration process itself incurs an additional time overhead. This paper proposes a heuristic method for designing customized multi-power domain reconfigurable scan networks with a minimized overall reconfiguration time. More precisely, the proposed method exploits a-priori given non-functional properties of the system, such as the power characteristics and the instruments’ access requirements. For the first time, these non-functional properties are considered to synthesize a well-adjusted and highly efficient multi-power domain network. The experimental results show a considerable improvement over the reported benchmark networks.

Abstract

Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing sys-tem-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

Abstract

Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.

Abstract

Machine learning (ML) has seen a strong rise in popularity in recent years and has become an essential tool for research and industrial applications. Given the large amount of high quality data needed and the often sensitive nature of ML data, privacy-preserving collaborative ML is of increasing importance. In this paper, we introduce new actively secure multiparty computation (MPC) protocols which are specially optimized for privacy-preserving machine learning applications. We concentrate on the optimization of (tensor) convolutions which belong to the most commonly used components in ML architectures, especially in convolutional neural networks but also in recurrent neural networks or transformers, and therefore have a major impact on the overall performance. Our approach is based on a generalized form of structured randomness that speeds up convolutions in a fast online phase. The structured randomness is generated with homomorphic encryption using adapted and newly constructed packing methods for convolutions, which might be of independent interest. Overall our protocols extend the state-of-the-art Overdrive family of protocols (Keller et al., EUROCRYPT 2018). We implemented our protocols on-top of MP-SPDZ (Keller, CCS 2020) resulting in a full-featured implementation with support for faster convolutions. Our evaluation shows that our protocols outperform state-of-the-art actively secure MPC protocols on ML tasks like evaluating ResNet50 by a factor of 3 or more. Benchmarks for depthwise convolutions show order-of-magnitude speed-ups compared to existing approaches.

Abstract

Some of the most efficient protocols for Multi-Party Computation (MPC) follow a two-phase approach where correlated randomness, in particular Beaver triples, is generated in the offline phase and then used to speed up the online phase. Recently, more complex correlations have been introduced to optimize certain operations even further, such as matrix triples for matrix multiplications. In this paper, our goal is to improve the efficiency of the triple generation in general and in particular for classical field values as well as matrix operations. To this end, we modify the Overdrive LowGear protocol to remove the costly sacrificing step and therewith reduce the round complexity and the bandwidth. We extend the state-of- the-art MP-SPDZ implementation with our new protocols and show that the new offline phase outperforms state-of-the-art protocols for the generation of Beaver triples and matrix triples. For example, we save 33 % in bandwidth compared to Overdrive LowGear.

Abstract

In recent years, actively secure SPDZ-like protocols for dishonest majority, like SPDZ2k, Overdrive2k, and MHz2k, over base rings Z2k have become more and more efficient. In this paper, we present a new actively secure MPC protocol Multipars that outperforms these state-of-the-art protocols over Z2k by more than a factor of 2 in the two-party setup in terms of communication. Multipars is the first actively secure N-party protocol over Z2k that is based on linear homomorphic encryption (LHE) in the offline phase (instead of oblivious transfer or somewhat homomorphic encryption in previous works). The strong performance of Multipars relies on a new adaptive packing for BGV ciphertexts that allows us to reduce the parameter size of the encryption scheme and the overall communication cost. Additionally, we use modulus switching for further size reduction, a new type of enhanced CPA security over Z2k, a truncation protocol for Beaver triples, and a new LHE-based offline protocol without sacrificing over Z2k. We have implemented Multipars and therewith provide the fastest preprocessing phase over Z2k. Our evaluation shows that Multipars offers at least a factor of 8 lower communication costs and up to a factor of 10.2 faster runtime in the WAN setting compared to the currently best available MPC implementation over Z2k.

Abstract

Some of the most efficient protocols for Multi-Party Computation (MPC) follow a two-phase approach where correlated randomness, in particular Beaver triples, is generated in the offline phase and then used to speed up the online phase. Recently, more complex correlations have been introduced to optimize certain operations even further, such as matrix triples for matrix multiplications. In this paper, our goal is to improve the efficiency of the triple generation in general and in particular for classical field values as well as matrix operations. To this end, we modify the Overdrive LowGear protocol to remove the costly sacrificing step and therewith reduce the round complexity and the bandwidth. We extend the state-of- the-art MP-SPDZ implementation with our new protocols and show that the new offline phase outperforms state-of-the-art protocols for the generation of Beaver triples and matrix triples. For example, we save 33 % in bandwidth compared to Overdrive LowGear.

Abstract

Reconfigurable Scan Networks (RSNs) access embedded instruments throughout the whole system lifecycle. To support dependability management by means of RSNs, RSNs themselves must be continuously tested. The paper-at-hand presents the first online periodic test method for RSNs. The developed algorithm generates a short sequence of test patterns, which tests all parts of an RSN. The generated sequence is uploaded on-chip and is applied periodically to avoid fault accumulation in RSNs. The overall test application time is minimized to comply with the timing requirements of the well-known safety standards. The experimental results show that the method is efficient for all considered RSN designs and is scalable with the increasing size and complexity of RSNs.

Abstract

Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications. Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high accuracy and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.

Abstract

Test methods that can keep up with the ongoing increase in complexity of semiconductor products and their underlying technologies are an essential prerequisite for maintaining quality and safety of our daily lives and for continued success of our economies and societies. There is a huge potential how test methods can benefit from recent breakthroughs in domains such as artificial intelligence, data analytics, virtual/augmented reality, and security. The Graduate School on “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR) at the University of Stuttgart is a large-scale, radically interdisciplinary effort to address the scientific-technological challenges in this domain. It is funded by Advantest, one of the world leaders in automatic test equipment. In this paper, we describe the overall philosophy of the Graduate School and the specific scientific questions targeted by its ten projects.

Abstract

Reconfigurable Scan Networks (RSNs) access the evaluation results from embedded instruments and control their operation throughout the device lifetime. At the same time, a single fault in an RSN may dramatically reduce the accessibility of the instruments. During post-silicon validation, it may prevent extracting the complete data from a device. During online operation, the inaccessibility of runtime-critical instruments via a defect RSN may eventually result in a system failure. This paper addresses both scenarios above by presenting robust RSNs. We show that by making a small number of carefully selected spots in RSNs more robust, the entire access mechanism becomes significantly more reliable. A flexible cost function assesses the importance of specific control primitives for the overall accessibility of the instruments. Following the cost function, a minimized number of spots is hardened against permanent faults. All the critical instruments as well as most of the remaining instruments remain accessible through the resulting RSNs even in the presence of defects. In contrast to state-of-the-art fault-tolerant RSNs, the presented approach does not change the RSN topology and needs less hardware overhead. Selective hardening is formulated as a multi-objective optimization problem and solved by using an evolutionary algorithm. The experimental results validate the efficiency and the scalability of the approach.

Abstract

In recent years, lattice-based secure multi-party computation (MPC) has seen a rise in popularity and is used more and more in large scale applications like privacy-preserving cloud computing, electronic voting, or auctions. Many of these applications come with the following high security requirements: a computation result should be publicly verifiable, with everyone being able to identify a malicious party and hold it accountable, and a malicious party should not be able to corrupt the computation, force a protocol restart, or block honest parties or an honest third-party (client) that provided private inputs from receiving a correct result. The protocol should guarantee verifiability and accountability even if all protocol parties are malicious. While some protocols address one or two of these often essential security features, we present the first publicly verifiable and accountable, and (up to a threshold) robust SPDZ-like MPC protocol without restart. We propose protocols for accountable and robust online, offline, and setup computations. We adapt and partly extend the lattice-based commitment scheme by Baum et al. (SCN 2018) as well as other primitives like ZKPs. For the underlying commitment scheme and the underlying BGV encryption scheme we determine ideal parameters. We give a performance evaluation of our protocols and compare them to state-of-the-art protocols both with and without our target security features: public accountability, public verifiability and robustness.

Abstract

Abstract Mutation testing is a technique that changes code instructions to assess the quality of automated software tests. Industry has not broadly adopted the technique because execution and analysis times are too long and not considered worth the effort. To change this, a variation called “extreme mutation testing” emerged, which mutates whole methods instead of instructions. The extreme variant trades accuracy for speed gains and also provides pre-analyzed results. In this study, we aim to analyze both techniques on their granularity levels, look for benefits when combining them, and find motivations when a developer considers killing mutants. For that, we conducted a case study in a company from the semiconductor industry. We mutated a large Java software project which is tested by more than 11,000 unit tests, analyzed the results, manually inspected more than 1000 mutants, and conducted a focus group with five developers of the software. Among other results, we provide the distribution of traditional across extreme mutants as well as qualitative coding results of our mutant inspection and focus group transcript. We conclude that the traditional approach can be similarly strategically applied as the extreme one and that motivations of developers to target mutants are mostly not code related.

Abstract

Reconfigurable Scan Networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side-channel. This paper presents an approach for Security Compliance Analysis and Resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented Security Compliance Analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes. As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.

Abstract

Some of the most efficient protocols for Multi-Party Computation (MPC) use a two-phase approach where correlated randomness, in particular Beaver triples, is generated in the offline phase and then used to speed up the online phase. Recently, more complex correlations have been introduced to optimize certain operations even further, such as matrix triples for matrix multiplications. In this paper, our goal is to speed up the evaluation of multivariate polynomials and therewith of whole arithmetic circuits in the online phase. To this end, we introduce a new form of correlated randomness: arithmetic tuples. Arithmetic tuples can be fine tuned in various ways to the constraints of application at hand, in terms of round complexity, bandwidth, and tuple size. We show that for many real-world setups an arithmetic tuples based online phase outperforms state-of-the-art protocols based on Beaver triples.

Abstract

Reconfigurable Scan Networks (RSNs) have to be tested before they can be used for post-silicon validation, diagnosis or online reliability management. Even a single stuck-at fault in the switch logic of an RSN can corrupt the scan paths and make instruments inaccessible. Testing the switch logic of an RSN is a complex sequential test problem. The existing test schemes for RSNs rely on the assumption that a fault in the switch logic will be detected by the altered length of the erroneously activated scan path. However, often this assumption does not hold and faults in the switch logic remain undetected. In this paper, an automated testability-enhancing resynthesis is presented. First, the testability of the initial RSN is accurately analyzed. If any single fault in the switch logic is undetectable by the altered path length, a small number of scan cells is inserted into the RSN. The presented scheme is applicable to arbitrary RSN designs and is compliant with state-of-the-art test methods and the applicable standards. The experimental results show the efficacy, the efficiency and the scalability of the approach.

Abstract

Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.

Abstract

Self-aware and safety-critical hardware/software systems rely on a variety of embedded instruments, sensors, monitors and design-for-test circuitry to check the system integrity. The access to these internal instruments is supported by standards commonly called iJTAG and employs so called reconfigurable scan networks (RSNs), which are more and more used at runtime, too. They collect periodically and also concurrently the information on the circuit’s health state and deliver it to some dependability management unit. The integrity of RSNs is essential for the dependability of selfaware systems and can be ensured by a combination of periodic and concurrent test methods of the RSN itself. The paper at hand presents the first concurrent online test method for RSNs by adding a brief integrity test to each access operation. The presented scheme includes a hardware extension of negligible size, supports offline test, diagnosis and post-silicon validation as well, and is further referred as ROSTI : RSN Online/Offline SelfTest Infrastructure. It exploits the original RSN control signals and does not require any modification of the underlying RSN. The hardware costs are independent of the size of the RSN, and ROSTI is flexible for generating different test sequences for different types of faults. The experimental results validate these characteristics and show that ROSTI is highly scalable.

Abstract

The reliable operation of integrated systems issupported by Reconfigurable Scan Networks (RSNs) which allow to access efficiently the embedded instruments throughout the life-cycle. However, the RSN integration may introduce additional connectivities into a Device-under-Test (DUT), and the RSN might be misused for information leakage. Structural methods resynthesize the RSNs and add hardware components such that certain instruments are physically separated, while functional approaches add filters to prevent certain access patterns. Both methods have certain limitations. This paper presents an effective approach to maximize the benefits and to overcome the limitations of the existing solutions by a hybrid combination of structural and functional protection schemes. A minimized number of structural changes is identified in order to resolve violations which cannot be handled by using sequence filters. The remaining violations are resolved functionally by using filters and a flexible protection can be enabled for multiple user groups with different access permissions. Since the majority of the violations are resolved using a filter, the hardware overhead for structural changes is drastically reduced. The efficiency of the approach is supported by experimental results.

Abstract

Reliable operation, test, debug and diagnosis of complex integrated systems are ensured by em-bedded instruments, such as sensors, aging monitors or Built-In Self-test (BIST) registers. Reconfigurable Scan Networks (RSNs) offer a flexible and efficient way to access such test instruments throughout the whole life-cycle. However, improper RSN integration might introduce additional connectivity properties to the device under test (DUT), which can be exploited to perform unauthorized access or cause information leakage. The existence of such additional connectivity through the RSN can compromise the security of the DUT and is considered as a security threat.In this paper, a method is presented to resolve all such security compliance violations. The problem is formulated in terms of Integer Linear Programming (ILP) as a minimum cut problem in multicommodity flow. An efficient heuristic is presented, which, to our knowledge, for the first time allows to consider the whole set of violations simultaneously and thereby to find a minimized number of changes to the RSN structure in order to make it compliant with the initial security requirements of the DUT and prevent the information leakage through the scan chain.