Publications

Abstract

Small Delay Faults (SDFs) introduce additional delays smaller than the capture time and require timing-aware test pattern generation. Since process variations can invalidate the effectivity of such patterns, different circuit instances may show a different fault coverage. This paper presents a method to generate test pattern sets for SDFs which are valid for all circuit timings. The method overcomes the complexity limitations of known timing-aware Automatic Test Pattern Generation (ATPG) which has to use fault sampling under process variations. A statistical learning scheme maximises the coverage of SDFs in an entire circuit population following the variation parameters of a calibrated industrial FinFET transistor model. The method combines efficient ATPG for Transition Faults with fast timing-aware fault simulation on GPUs. Experiments show that the size of the pattern set is significantly reduced in comparison to standard N-detect while the fault coverage even increases compared to both N-detect and timing-aware ATPG

Abstract

The Preconditioned Conjugate Gradient (PCG) method is well-established for solving linear equations systems. Running the PCG method on a hardware accelerator ensures fast and efficient computation. At the same time, each hardware accelerator may be slightly different due to process variability or aging. To handle the variability, a rather pessimistic frequency selection for the whole population of accelerators is often utilized. Increasing the frequency may improve the performance but may also increase the risk of computational errors, affect the convergence of PCG or even corrupt the PCG results. In this paper, we present a method to determine the frequency for each hardware accelerator instance which optimizes the execution time and the energy efficiency of the PCG method. First, a technique is presented to analyze the error resilience of a PCG algorithm to overclocking. Based on the analysis results, we increase the frequency to speed up the convergence while keeping the error rate below the required threshold.

Abstract

Many applications from Artificial Intelligence (AI) and Scientific Computing rely on efficient algorithms for solving large systems of linear equations. The Preconditioned Conjugate Gradient (PCG) algorithm is a promising option and it is a perfect candidate to be executed on specialized hardware accelerators widely used in AI. Hardware accelerators, like other modern devices, are prone to process variations. A conventional approach to handle the variability is to use pessimistic guard�bands for all the devices within the population, which implies that the best and even the average accelerators are slowed down significantly. Since the PCG algorithm is inherently error resilient to some extent, it may also tolerate an error rate increase due to overclocking. On another side, increasing the frequency may increase the total execution time if more arithmetic operations are needed until the convergence. This paper presents a method to ensure efficient computing on each hardware accelerator instance running the PCG algorithm. A cross-layer approach identifies an optimized frequency that minimizes the total time to complete the PCG algorithm. Simple high-level checks ensure the quality of the solution. Experimental results validate the feasibility of the developed approach for large systems of linear equations.

Abstract

The high-volume manufacturing test ensures the production of defect-free devices, which is of utmost importance when dealing with safety-critical systems. Such a high-quality test requires a deliberately designed scan network to provide a time and cost-effective access to many on-chip components, as included in state-of-the-art chip designs. The IEEE 1687 Std. (IJTAG) has been introduced to tackle this challenge by adding programmable components that enables the design of reconfig- urable scan networks. Although these networks reduce the test time by shortening the scan chains’ lengths, the reconfiguration process itself incurs an additional time overhead. This paper proposes a heuristic method for designing customized multi-power domain reconfigurable scan networks with a minimized overall reconfiguration time. More precisely, the proposed method exploits a-priori given non-functional properties of the system, such as the power characteristics and the instruments’ access requirements. For the first time, these non-functional properties are considered to synthesize a well-adjusted and highly efficient multi-power domain network. The experimental results show a considerable improvement over the reported benchmark networks.

Abstract

Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing sys-tem-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

Abstract

Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.

Abstract

Reconfigurable Scan Networks (RSNs) access embedded instruments throughout the whole system lifecycle. To support dependability management by means of RSNs, RSNs themselves must be continuously tested. The paper-at-hand presents the first online periodic test method for RSNs. The developed algorithm generates a short sequence of test patterns, which tests all parts of an RSN. The generated sequence is uploaded on-chip and is applied periodically to avoid fault accumulation in RSNs. The overall test application time is minimized to comply with the timing requirements of the well-known safety standards. The experimental results show that the method is efficient for all considered RSN designs and is scalable with the increasing size and complexity of RSNs.

Abstract

Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications. Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high accuracy and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.

Abstract

Reconfigurable Scan Networks (RSNs) access the evaluation results from embedded instruments and control their operation throughout the device lifetime. At the same time, a single fault in an RSN may dramatically reduce the accessibility of the instruments. During post-silicon validation, it may prevent extracting the complete data from a device. During online operation, the inaccessibility of runtime-critical instruments via a defect RSN may eventually result in a system failure. This paper addresses both scenarios above by presenting robust RSNs. We show that by making a small number of carefully selected spots in RSNs more robust, the entire access mechanism becomes significantly more reliable. A flexible cost function assesses the importance of specific control primitives for the overall accessibility of the instruments. Following the cost function, a minimized number of spots is hardened against permanent faults. All the critical instruments as well as most of the remaining instruments remain accessible through the resulting RSNs even in the presence of defects. In contrast to state-of-the-art fault-tolerant RSNs, the presented approach does not change the RSN topology and needs less hardware overhead. Selective hardening is formulated as a multi-objective optimization problem and solved by using an evolutionary algorithm. The experimental results validate the efficiency and the scalability of the approach.

Abstract

Abstract Mutation testing is a technique that changes code instructions to assess the quality of automated software tests. Industry has not broadly adopted the technique because execution and analysis times are too long and not considered worth the effort. To change this, a variation called “extreme mutation testing” emerged, which mutates whole methods instead of instructions. The extreme variant trades accuracy for speed gains and also provides pre-analyzed results. In this study, we aim to analyze both techniques on their granularity levels, look for benefits when combining them, and find motivations when a developer considers killing mutants. For that, we conducted a case study in a company from the semiconductor industry. We mutated a large Java software project which is tested by more than 11,000 unit tests, analyzed the results, manually inspected more than 1000 mutants, and conducted a focus group with five developers of the software. Among other results, we provide the distribution of traditional across extreme mutants as well as qualitative coding results of our mutant inspection and focus group transcript. We conclude that the traditional approach can be similarly strategically applied as the extreme one and that motivations of developers to target mutants are mostly not code related.

Abstract

Reconfigurable Scan Networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side-channel. This paper presents an approach for Security Compliance Analysis and Resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented Security Compliance Analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes. As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.

Abstract

Reconfigurable Scan Networks (RSNs) have to be tested before they can be used for post-silicon validation, diagnosis or online reliability management. Even a single stuck-at fault in the switch logic of an RSN can corrupt the scan paths and make instruments inaccessible. Testing the switch logic of an RSN is a complex sequential test problem. The existing test schemes for RSNs rely on the assumption that a fault in the switch logic will be detected by the altered length of the erroneously activated scan path. However, often this assumption does not hold and faults in the switch logic remain undetected. In this paper, an automated testability-enhancing resynthesis is presented. First, the testability of the initial RSN is accurately analyzed. If any single fault in the switch logic is undetectable by the altered path length, a small number of scan cells is inserted into the RSN. The presented scheme is applicable to arbitrary RSN designs and is compliant with state-of-the-art test methods and the applicable standards. The experimental results show the efficacy, the efficiency and the scalability of the approach.

Abstract

Small Delay Faults (SDFs) due to defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is in the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its behavioral features are affected by several masking impacts of the rest of the circuit. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defect devices without a major impact on yield.

Abstract

Self-aware and safety-critical hardware/software systems rely on a variety of embedded instruments, sensors, monitors and design-for-test circuitry to check the system integrity. The access to these internal instruments is supported by standards commonly called iJTAG and employs so called reconfigurable scan networks (RSNs), which are more and more used at runtime, too. They collect periodically and also concurrently the information on the circuit’s health state and deliver it to some dependability management unit. The integrity of RSNs is essential for the dependability of selfaware systems and can be ensured by a combination of periodic and concurrent test methods of the RSN itself. The paper at hand presents the first concurrent online test method for RSNs by adding a brief integrity test to each access operation. The presented scheme includes a hardware extension of negligible size, supports offline test, diagnosis and post-silicon validation as well, and is further referred as ROSTI : RSN Online/Offline SelfTest Infrastructure. It exploits the original RSN control signals and does not require any modification of the underlying RSN. The hardware costs are independent of the size of the RSN, and ROSTI is flexible for generating different test sequences for different types of faults. The experimental results validate these characteristics and show that ROSTI is highly scalable.

Abstract

The reliable operation of integrated systems issupported by Reconfigurable Scan Networks (RSNs) which allow to access efficiently the embedded instruments throughout the life-cycle. However, the RSN integration may introduce additional connectivities into a Device-under-Test (DUT), and the RSN might be misused for information leakage. Structural methods resynthesize the RSNs and add hardware components such that certain instruments are physically separated, while functional approaches add filters to prevent certain access patterns. Both methods have certain limitations. This paper presents an effective approach to maximize the benefits and to overcome the limitations of the existing solutions by a hybrid combination of structural and functional protection schemes. A minimized number of structural changes is identified in order to resolve violations which cannot be handled by using sequence filters. The remaining violations are resolved functionally by using filters and a flexible protection can be enabled for multiple user groups with different access permissions. Since the majority of the violations are resolved using a filter, the hardware overhead for structural changes is drastically reduced. The efficiency of the approach is supported by experimental results.

Abstract

Reliable operation, test, debug and diagnosis of complex integrated systems are ensured by em-bedded instruments, such as sensors, aging monitors or Built-In Self-test (BIST) registers. Reconfigurable Scan Networks (RSNs) offer a flexible and efficient way to access such test instruments throughout the whole life-cycle. However, improper RSN integration might introduce additional connectivity properties to the device under test (DUT), which can be exploited to perform unauthorized access or cause information leakage. The existence of such additional connectivity through the RSN can compromise the security of the DUT and is considered as a security threat.In this paper, a method is presented to resolve all such security compliance violations. The problem is formulated in terms of Integer Linear Programming (ILP) as a minimum cut problem in multicommodity flow. An efficient heuristic is presented, which, to our knowledge, for the first time allows to consider the whole set of violations simultaneously and thereby to find a minimized number of changes to the RSN structure in order to make it compliant with the initial security requirements of the DUT and prevent the information leakage through the scan chain.