44. Online Periodic Test of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In To appear in Proceedings of the IEEE Asian Test Symposium, Taichung, Taiwan, 2022, pp. 1--6.
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Reconfigurable Scan Networks (RSNs) access embedded instruments throughout the whole system lifecycle. To support dependability management by means of RSNs, RSNs themselves must be continuously tested. The paper-at-hand presents the first online periodic test method for RSNs. The developed algorithm generates a short sequence of test patterns, which tests all parts of an RSN. The generated sequence is uploaded on-chip and is applied periodically to avoid fault accumulation in RSNs. The overall test application time is minimized to comply with the timing requirements of the well-known safety standards. The experimental results show that the method is efficient for all considered RSN designs and is scalable with the increasing size and complexity of RSNs.BibTeX
43. Brain-Inspired Hyperdimensional Computing for Ultra-Efficient Edge AI. Hussam Amrouch; Mohsen Imani; Xun Jiao; Yiannis Aloimonos; Cornelia Fermuller; Dehao Yuan; Dongning Ma; Hamza Errahmouni; Paul R. Genssler and Peter Sutor. In Proceedings of the 2022 International Conference on Hardware/Software Codesign and System Synthesis, 2022.
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42. Cross-layer FeFET Reliability Modeling towards Robust Hyperdimensional Computing. Shubham Kumar; Swetaki Chatterjee; Simon Thomann; Paul R. Genssler; Yogesh S. Chauhan and Hussam Amrouch. In IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC’22), 2022.
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41. Mitigating the Complexity of Chip Designs with ML-based Cell Library Characterization. Florian Klemme and Hussam Amrouch. In Workshop on Intelligent Methods for Test and Reliability (IMTR’22), 2022.
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40. On Extracting Reliability Information from Speed Binning. Zahra Paria Najafi-Haghi; Florian Klemme; Hussam Amrouch and Hans-Joachim Wunderlich. In
Proceedings of the 27th IEEE European Test Symposium (ETS’22), Barcelona, Spain, 2022. DOI:
https://doi.org/10.1109/ETS54262.2022.9810443 Abstract
Adaptive Voltage Frequency Scaling (AVFS) is an important means to overcome process-induced variability challenges for advanced high-performance circuits. AVFS requires and allows determining the maximum speed Fmax(Vdd) reachable under a set of certain operation voltages Vdd. In this paper, it is shown that the Fmax(Vdd) measurements contain relevant data to identify some hidden defects in a chip which are reliability threats and can cause device failures, but pass the speed binning procedure within the given specifications.
Static Timing Analysis (STA) is applied to a circuit designed by using standard cell libraries in which the underlying transistors along with process variations have been carefully calibrated against industrial 14nm FinFET measurement data, and instances with and without injected small resistive open defects are generated. From the slope of the function Fmax(Vdd), a machine learning procedure can identify some defects with high accuracy and few false positives. These chips can be then discarded without any further need and cost for testing. It has to be noted that this reliability information comes for free from the data which is already generated, and does not need any additional measurements.BibTeX
39. Intelligent Methods for Test and Reliability. Hussam Amrouch; Jens Anders; Steffen Becker; Maik Betka; Gerd Bleher; Peter Domanski; Nourhan Elhamawy; Thomas Ertl; Athanasios Gatzastras; Paul R. Genssler; Sebastian Hasler; Martin Heinrich; André van Hoorn; Hanieh Jafarzadeh; Ingmar Kallfass; Florian Klemme; Steffen Koch; Ralf Küsters; Andrés Lalama; Raphael Latty; Yiwen Liao; Natalia Lylina; Zahra Paria Najafi-Haghi; Dirk Pflüger; Ilia Polian; Jochen Rivoir; Matthias Sauer; Denis Schwachhofer; Steffen Templin; Christian Volmer; Stefan Wagner; Daniel Weiskopf; Hans-Joachim Wunderlich; Bin Yang and Martin Zimmermann. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, 2022, pp. 1–6.
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38. Self-learning tuning for post-silicon validation. Peter Domanski; Dirk Pflüger; Jochen Rivoir and Raphael Latty. In 34. GI / GMM / ITG-Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (TuZ’22)), 2022.
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37. Robust Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich. In
Proceedings of the Conference on Design, Automation and Test in Europe (DATE’22), Antwerp, Belgium, 2022, pp. 1--4. DOI:
https://doi.org/10.23919/DATE54114.2022.9774770 Abstract
Reconfigurable Scan Networks (RSNs) access the evaluation results from embedded instruments and control their operation throughout the device lifetime. At the same time, a single fault in an RSN may dramatically reduce the accessibility of the instruments. During post-silicon validation, it may prevent extracting the complete data from a device. During online operation, the inaccessibility of runtime-critical instruments via a defect RSN may eventually result in a system failure. This paper addresses both scenarios above by presenting robust RSNs. We show that by making a small number of carefully selected spots in RSNs more robust, the entire access mechanism becomes significantly more reliable. A flexible cost function assesses the importance of specific control primitives for the overall accessibility of the instruments. Following the cost function, a minimized number of spots is hardened against permanent faults. All the critical instruments as well as most of the remaining instruments remain accessible through the resulting RSNs even in the presence of defects. In contrast to state-of-the-art fault-tolerant RSNs, the presented approach does not change the RSN topology and needs less hardware overhead. Selective hardening is formulated as a multi-objective optimization problem and solved by using an evolutionary algorithm. The experimental results validate the efficiency and the scalability of the approach.BibTeX
36. Machine Learning for Reliability-Aware, yet Confidential Standard Cell Characterization. Florian Klemme and Hussam Amrouch. In The 34th Workshop on Test Methods and Reliability of Circuits and Systems (TuZ’22), 2022.
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35. Design Close to the Edge in Advanced Technology using Machine Learning and Brain-Inspired Algorithms. Hussam Amrouch; Florian Klemme and Paul R. Genssler. In 27th Asia and South Pacific Design Automation Conference (ASP-DAC’22), 2022.
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34. Towards practical application of mutation testing in industry — Traditional versus extreme mutation testing. Maik Betka and Stefan Wagner.
Journal of Software: Evolution and Process (2022), pp. e2450. DOI:
https://doi.org/10.1002/smr.2450 Abstract
Abstract Mutation testing is a technique that changes code instructions to assess the quality of automated software tests. Industry has not broadly adopted the technique because execution and analysis times are too long and not considered worth the effort. To change this, a variation called “extreme mutation testing” emerged, which mutates whole methods instead of instructions. The extreme variant trades accuracy for speed gains and also provides pre-analyzed results. In this study, we aim to analyze both techniques on their granularity levels, look for benefits when combining them, and find motivations when a developer considers killing mutants. For that, we conducted a case study in a company from the semiconductor industry. We mutated a large Java software project which is tested by more than 11,000 unit tests, analyzed the results, manually inspected more than 1000 mutants, and conducted a focus group with five developers of the software. Among other results, we provide the distribution of traditional across extreme mutants as well as qualitative coding results of our mutant inspection and focus group transcript. We conclude that the traditional approach can be similarly strategically applied as the extreme one and that motivations of developers to target mutants are mostly not code related.BibTeX
33. Efficient and Robust Resistive Open Defect Detection based on Unsupervised Deep Learning. Yiwen Liao; Zahra Paria Najafi-Haghi; Hans-Joachim Wunderlich and Bin Yang. In IEEE International Test Conference (ITC), Anaheim, USA, 2022.
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32. Conditional Variable Selection for Intelligent Test. Yiwen Liao; Tianjie Ge; Raphaël Latty and Bin Yang. In 1st Workshop on Intelligent Methods for Test and Reliability, co-organized with IEEE European Test Symposium (ETS’22), Barcelona, Spain, 2022.
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31. Scalable Machine Learning to Estimate the Impact of Aging on Circuits under Workload Dependency. Florian Klemme and Hussam Amrouch. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022).
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30. Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries. Florian Klemme and Hussam Amrouch.
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022). DOI:
https://doi.org/10.1109/TCSI.2022.3201431 BibTeX
29. SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks. Natalia Lylina; Chih-Hao Wang and Hans-Joachim Wunderlich.
Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (2022), pp. 1--14. DOI:
https://doi.org/10.1109/TCAD.2022.3158250 Abstract
Reconfigurable Scan Networks (RSNs) enable an efficient reliability management throughout the device lifetime. They can be used for controlling integrated instruments, such as aging monitors or built-in self-test (BIST) registers, as well as for collecting the evaluation results from them. At the same time, they may impose a security threat, since the additional connectivities introduced by the RSN can possibly be misused as a side-channel.
This paper presents an approach for Security Compliance Analysis and Resynthesis (SCAR) of RSNs to integrate an RSN compliant with the security properties of the initial design. First, the reachability properties of the original design are accurately computed. The connectivities inside the RSN, which exceed the allowed connectivity of the initial design, are identified using the presented Security Compliance Analysis. Next, all violations are resolved by automated Resynthesis with a minimized number of structural changes.
As a result of SCAR, any information leakage due to the RSN integration is prevented, while the accessibility of the instruments through the RSN is preserved. The approach is able to analyze complex control dependencies and obtains a compliant RSN even for the largest available benchmarks.BibTeX
28. Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing? Paul Genssler; Austin Vas and Hussam Amrouch. IEEE Embedded Systems Letters (ESL’22) (2022).
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27. Variability-Aware Approximate Circuit Synthesis via Genetic Optimization. Konstantinos Balaskas; Florian Klemme; Georgios Zervakis; Kostas Siozios; Hussam Amrouch and Jörg Henkel. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I) (2022).
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26. All-in-Memory Brain-Inspired Computing using FeFET Synapses. Simon Thomann; Nguyen Hong Lam Giang; Paul R. Genssler and Hussam Amrouch.
Frontiers in Electronics (2022). DOI:
https://doi.org/10.3389/felec.2022.833260 BibTeX
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24. To Generalize or Not to Generalize: Towards Autoencoders in One-Class Classification. Yiwen Liao and Bin Yang. In International Joint Conference on Neural Networks (IJCNN) and IEEE World Congress on Computational Intelligence (WCCI), Padua, Italy, 2022.
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23. GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation. Lilas Alrahis; Johann Knechtel; Florian Klemme; Hussam Amrouch and Ozgur Sinanoglu. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD’22), ESWEEK Special Issue (2022).
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22. Wafer Map Defect Identification Based on the Fusion of Pattern and Pixel Information. Yiwen Liao; Raphael Latty; Paul R. Genssler; Hussam Amrouch and Bin Yang. In IEEE International Test Conference (ITC’22), 2022.
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21. A Deep-Learning-Aided Pipeline for Efficient Post-Silicon Tuning. Yiwen Liao; Jochen Rivoir; Raphaël Latty and Bin Yang. In In the 34th Workshop on Test Methods and Reliability of Circuits and Systems (TuZ 2022), Bremerhaven, Germany, 2022.
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