Open Positions

Description of open PhD positions

PhD Positions

The Graduate School “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR) at the University of Stuttgart in cooperation with ADVANTEST invites in its second funding phase applications for

10 full-time PhD positions (research assistant, 100% TV-L E13) for 3 years starting in April 2023.

The GS-IMTR is an interdisciplinary graduate school combining research expertise from computer science, electrical engineering, information technology, and beyond. GS-IMTR is Germany's first industry-funded Graduate School, established in cooperation with ADVANTEST, a major global manufacturer of automatic test equipment for integrated circuits. Its overall aim is to develop new methods for topics such as design for test and diagnosis; post-silicon validation; test generation and optimization; robust device tuning; system-level test; lifetime test and reliability management; security, privacy and reliability of testing; test for advanced and emerging technologies and test automation. A modern understanding of these topics demands novel artificial intelligence methods and has tight connections to data science, data analytics, data understanding, machine learning, security, and privacy.

A structured doctoral program includes a supervision concept, mentorship from Advantest, measures for international mobility and a research stay abroad, as well as a tailored qualification program with subject-based and soft-skill courses.

Positions are being offered in the following 10 research projects, for details about each project see below:

  • Virtual Test for mixed-signal Circuits: Digital Twin based Development of Post-Silicon Tests
  • Enhancing Test Methods by Magnetic Fields
  • Over-the-Air (OTA) production-test concepts for future millimeter-wave antenna array
    modules
  • Intelligent Sensing and On-Chip Learning for Silicon Lifecyle
  • Test and Reliability Challenges for Advanced Sub-5nm Technologies
  • Novel Test Methods for Emerging and Classical Memories using Magnetic Field
  • Variable selection with automated feature design for post- silicon validation and production
  • Automatic and Dynamic Tuning beyond Post-Silicon Validation
  • Explanations for Failures from Software Testing
  • Privacy-Preserving Machine Learning for Semiconductor Testing

Applicants should hold a master’s or equivalent degree in electrical engineering, computer science, information technology, mathematics, physics, or a related discipline with above-average results. They are expected to show a high level of proficiency in both spoken and written English.

Please send your application (cover letter, academic CV, letter of motivation indicating your favorite project(s), degree certificates and transcripts of records from Bachelor/Master, names of potential academic referees) either electronically in a single PDF file (up to 10 MB) addressed to the corresponding project lead(s) to application-gs-imtr@ipvs.uni-stuttgart.de, or by classical mail to

Prof. Dr. Dirk Pflüger
Institute for Parallel and Distributed Systems
Universitätsstr. 38
70569 Stuttgart
Germany

until January 29 2023. Information in accordance with Article 13 DS-GVO on the processing of applicant data can be found at https://careers.uni-stuttgart.de/content/privacy-policy/?locale=en_US.

We will indicate on the website which positions have already been filled; later applications might be accepted.

Project lead(s)
  • Andrey Morozov and Michael Weyrich
What we are looking for:
  • MSc in electrical engineering, computer science, mathematics, or a related field
  • Strong mathematical skills and embedded programming experience
  • Knowledge of system modeling, simulation, and Digital Twin concepts
  • Understanding of digital and mixed-signal circuits
  • Understanding of microelectronics diagnosis, including fault modeling, fault simulation, test pattern generation
Abstract

This project is devoted to Digital-Twin based methods for earlier development of optimized post-silicon tests for chips with mixed-signal circuits. Post-manufacturing testing, like wafer testing and final testing of chips, ensures that each chip delivered contains no manufacturing defects that harm its functionality. Although mixed-signal circuits make up only a relatively small number of the circuits integrated into a chip, the development of tests for chips that also feature mixed-signal circuits takes a disproportionately long time. Today, the development of corresponding tests starts only after the production of the first chips. According to our vision, implementing the post-manufacturing or so-called post-silicon tests should be started before producing the first chips. This will accelerate time-to-market and enables parts of the Test Program development before the first physical devices are available. For this objective, we will use the Digital Twin of a chip, i.e., an extensive software system that leverages models and data of an original chip to represent, predict, and simulate its behavior for test generation purposes. This willrequire the adaptation and extension of the so- called Virtual Test infrastructure, which is today in use for pre-silicon validation needs, for the earlier post-manufacturing test development requirements. Furthermore, such a Digital Twin environment will optimize post-silicon test scheduling. Today, mixed-signal post-silicon tests are usually performed sequentially using automated test equipment, so-called testers. By modeling post-silicon test constraints, an optimal parallel schedule can be obtained.

Project lead(s)
What we are looking for:

A successful candidate is expected to have in-depth knowledge in the following areas listed below:

  • Semiconductor device physics.
  • In-depth knowledge in test methods for digital circuits will be considered an additional asset.
  • Transistor device modeling and compact modeling.
  • Solid skills in both SPICE simulations as well as in Technology CAD (TCAD) tool flows.
  • Basic to gool skills in VLSI design.
  • Good programming skills and in particular the Python language.
Abstract

In this project, we will consider digital combinational CMOS logic and investigate the responses of defective structures under static and dynamic magnetic fields in three domains: logical (changes in the digital Boolean function); timing (impact on the observable delay); and current (quiescent and transient IDD). In addition, we will explore our methods for emerging devices.

Project lead(s)
  • Jan Hesselbarth
What we are looking for:
  • You are a creative and enthusiastic team player.
  • You should possess a very good Master degree in electronics (or, in a similar field) and reasonable knowledge in radio frequency technology (or, microwaves and electromagnetics).
  • You are skilled in use of CST and/or HFSS software.
  • You have a high level of proficiency in spoken and written English.
Abstract

Transceiver front-ends for millimeter-wave wireless communications, such as driven by 5G and 6G systems, are  increasingly integrated together with antenna arrays within compact module form factors. The production test and calibration of such modules requires new over-the-air (OTA) measurement concepts. This project shall investigate new OTA concepts, addressing electromagnetic and antenna aspects as well as strategies and requirements for test and calibration of large arrays.

Project lead(s)
What we are looking for:

A successful candidate is expected to have in-depth knowledge in the following areas listed below:

  • Solid background in mixed-signal IC design
  • Very good skills in circuit design and implementation using tool flows from Synopsys or Cadence.
  • Solid background in computer architecture.
  • Good programming skills, including a good background in Python.
Abstract

This project explores the challenges that silicon lifecycle management introduces into the chip design process and, more importantly, the opportunities that it brings to the area of test. In particular, we will focus on the possibilities associated with digital on-chip sensors combined with edge AI in the tester to collect and process the data very efficiently at run-time. Further, we will also investigate the possibility of on-chip online learning on the collected data.

Project lead(s)
What we are looking for:

A successful candidate is expected to have in-depth knowledge in the following areas listed below:

  • Semiconductor device physics.
  • Transistor device modeling and compact modeling.
  • Solid skills in both SPICE simulations as well as in Technology CAD (TCAD) tool flows.
  • Bassic to gool skills in VLSI design.
  • Good programming skills and in particular the Python language.
Abstract

The research will be focused on the advanced technology nodes of transistors at the 5nm, 3nm and 2nm in which new 3D structures are employed as well as new gate materials like hafnium zirconium are used. We will focus on several reliability problems such transistor self-heating and transistor aging. We will also focus on developing novel test methods for the purpose of improving IC yield in latest advanced technology node.

Project lead(s)
What we are looking for:

A successful candidate is expected to have in-depth knowledge in the following areas listed below:

  • Semiconductor device physics.
  • Transistor device modeling and compact modeling.
  • Solid skills in both SPICE simulations as well as in Technology CAD (TCAD) tool flows.
  • Skills (optional) in COMSOL and/or ANSYS multi-physics simulations.
  • Basic to gool skills in VLSI design.
  • Good programming skills and in particular the Python language.
Abstract

We will focus on studying the interactions between semiconductor device physics and external magnetic fields. The studies will be carried out for both transistors and memory cells. Emerging technology nodes and in particular the ferroelectric memories will be in detail investigated.

Project lead(s)
  • Bin Yang
What we are looking for:

MSc graduate in electrical engineering, computer science, mathematics, data science or a related field

  • Strong mathematical skills
  • Profound deep learning skills
  • Programming experience (preferably Tensorflow/Pytorch)
  • Knowledge of variable selection
Abstract

Feature selection in machine learning (ML) in general or variable selection in semiconductor test deal with the problem of selecting a subset from a large number of input features or variables. In this proposal, we use the term variable selection because the input quantities under consideration, i.e. the stimuli, operational conditions and tuning knobs during PSV, are mostly measured physical variables (e.g. voltage, current, power, frequency, time) and not features calculated from raw data.

Variable selection can be supervised or unsupervised. In this project, variable selection is supervised because we aim to select input variables to best predict one or a few target variables. The current approach in PSV, which is addressed in our previous project, is to select 3 to 5 relevant input variables from up to a few hundreds. The test engineers plot one target variable as a function of the selected input variables and use this visualization in debugging the DUT (which variables cause the DUT to fail?) or tuning (which variables influence the performance of the DUT most?).

Project lead(s)
  • Dirk Pflüger
What we are looking for:
  • A very good MSc graduate in computer science, mathematics, data science, electrical engineering or a related field
  • Strong mathematical skills
  • Profound programming experience (preferably Python)
  • Knowledge of Machine Learning, e.g., dimensionality reduction, high-dimensional approximation, reinforcement learning, or parameter identification are an asset
Abstract

Performance tuning of semiconductors plays an important role in testing since it is decisive for the yield in production and time-to-market. As produced chips necessarily deviate from their specs, for example due to highly complex designs and tight process integration, tuning has to ensure that their observed performance stays within their specifications under all allowed (environmental) conditions. Robustperformance tuning poses a complicated optimization setting with peculiar challenges. In a previous project, we have developed a novel approach, where an efficient and flexbile tuning law is learned with reinforcement learning that is robust against faulty devices in the training data.

The current setting is that of Post-Silicon Validation, where learning is based on test data for a first batch of produced chips. This project will extend the current static setting to dynamic scenarios. The aim is intelligent tuning that continuously adapts to shifts in the data, for example due to process variation and changing conditions in high-volume production. This raises challenging questions, for example of how to adapt machine learning models without full re-training, and how to deal with non-standard data. You will approach these questions for example with methods from active learning, reinforcement learning, and higher-dimensional approximation.

Project lead(s)
  • Stefan Wagner, Steffen Becker
What we are looking for:
  • MSc in software engineering, computer science or related fields
  • Strong background in programming, software engineering and ideally in software testing and analysis
  • Fluent in spoken and written English
  • Creative thinker and independent work style
Abstract

High-quality test software is critical for high-quality hardware testing. Complex software plays a vital role in large-scale hardware testing. Test programs allow hardware testers to deal with the complexity of modern chips and enable them to automate the tests. Yet, the software itself also becomes large and complex leading to hard to understand failures. In this project, you will develop methods and tools to support software testers in understanding failures that are uncovered during software testing. For this, you will explain these failures by the context and possible influencing factors, the executed code and possible code fixes. The method and tool development will iteratively validated using empirical studies.

Project lead(s)
  • Ralf Küsters
What we are looking for:
  •  
Abstract

Over the past two decades the semiconductor industry has shifted from an integrated device manufacturer (IDM) dominated market towards the fabless model with its multitude of highly specialized service providers such as foundries, fabless designers, test houses, and electronic design automation (EDA) software providers. During the production process, large amounts of data are generated and have to be analyzed and monitored, e.g. data from fabrication equipment, measurements from the testing process, or supplementary data from managing the production process itself.

In order to analyze this data, techniques based on machine learning (ML) are increasingly employed. Applications for ML in the semiconductor production include among others to predict the later behavior of devices based on early data and to improve the classification of devices during tests (i.e. binning). However, a large amount of the currently generated data is sensitive and the data owners are unwilling to share this data without security and privacy guarantees, since it contains insights into business-critical information such as yield, characteristics of devices, and operational parameters. This information needs to be protected from unwanted disclosure or industrial espionage. Besides intellectual property issues, the data may also involve customer data which cannot be forwarded to ML service providers legally.

The goal of this project is therefore to enable parties in the semiconductor production chain to carry out ML computations on large data sets in a federated but privacy-preserving way, i.e., in a way where parties do not need to reveal their data or models to other parties. For this purpose, cryptographic techniques, in particular, multi-party computation (MPC), are used, adapted, and further developed.

Contact

This image shows Dirk Pflüger

Dirk Pflüger

Prof. Dr. rer. nat.

Institute for Parallel and Distributed Systems (IPVS)

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