Open Positions

Description of open PhD positions

PhD Positions

The newly established Graduate School “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR) at the University of Stuttgart in cooperation with ADVANTEST invites applications for full-time PhD positions (research assistant) for 3 years with a possibility for extension, 100% TV-L E13 to begin as soon as possible in 2020. Its overall aim is to develop new methods for topics such as design for test and diagnosis; post-silicon validation; test generation and optimization; robust device tuning; system-level test; lifetime test and reliability management; and test automation. A modern understanding of these topics demands novel artificial intelligence methods and has tight connections to data science, data analytics, data understanding, visualization, security, and privacy.

We provide an excellent research environment with the GS-IMTR, the cooperation with ADVANTEST, and within the respective institutes.

In the following, you can find a list of the remaining PhD positions to be installed:

Project lead

Thomas Ertl, Steffen Koch, Daniel Weiskopf

We are looking for

A motivated applicant with a very good master’s degree in computer science or related disciplines. The candidate should have strong programming skills. A background in visualization, data analysis, machine learning, or a combination thereof is beneficial.

Project summary

This project aims to tackle challenges occurring in post-silicon validation with visual analytics methods. Visual analytics helps users analyze complex problems iteratively and supports the steering of complex analysis processes. It therefore constitutes a valid approach to address some of the difficult problems occurring in post-silicon analysis. These include the comparison of high-dimensional test parameters and output parameter spaces, the sparseness of errors and resulting difficulties to develop hypotheses on problem causes, as well as the validation of hypotheses including the generation of new test parameters if necessary.

The project’s goal is to develop new visual analytics approaches in close cooperation with chip testing experts, and to organize successful visual solutions into coherent interactive analysis workflows.

The research in this project is planned to lead to a doctoral thesis in computer science, focusing on visualization and visual analytics. To support successful research for the thesis, we provide an excellent research environment with the Graduate School “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR), the cooperation with ADVANTEST, as well as with the Institute for Visualization and Interactive Systems (VIS) and the Visualization Research Center (VISUS) at the University of Stuttgart.

Project lead

Dirk Pflüger

What we are looking for:
  • MSc graduate in computer science, mathematics, data science, electrical engineering or a related field
  • Strong mathematical skills
  • Programming experience (preferably Python and/or C++)
  • Knowledge of dimensionality reduction, parameter identification, high-dimensional approximation, or inverse problems are an asset
Abstract

The generation of meaningful test sets in semiconductor testing plays an important role to fast and cost-efficient testing. The goal of this project is to improve beyond pure stochastic sampling which provides valid though very large test sets. We will therefore develop a (semi-)automatic methodological framework for the self-learning generation of meaningful test sets and their analysis.
The project strives to provide guided, intelligent sampling of the parameter space of the test function based on the analysis of the currently gathered data. The aim is to add test cases to best increase the information gain about the exploration of the input space, combining, for example, methods from statistics, big data, and higher-dimensional approximation.

Project lead

Ralf Küsters

What we are looking for:
  • MSc graduate in computer science, mathematics, cyber security, or a related field
  • Strong mathematical skills
  • Knowledge of cryptography, in particular, multi-party computation, zero-knowledge proofs, and/or fully homomorphic encryption is an asset
Abstract

Semiconductor testing plays an important role in the semiconductor manufacturing process. The tests not only ensure the quality of individual chips, but the data obtained during the tests is used to improve the manufacturing process itself. Often manufacturers use third-party services to perform the tests and evaluate the test data, as this requires specialized expertise. Since the test data and the models and methods to evaluate the data, such as machine learning models, are typically highly sensitive trade secrets, on the one hand, manufacturers are reluctant to share their test data with third-party evaluation services, and on the other hand, the services do not want to reveal their evaluation models and methods.

The idea of the project is to use, further develop, and adapt secure cryptographic protocols, to protect the digital assets in a globalized and distributed semiconductor manufacturing flow.

Project lead:

Steffen Becker, Ilia Polian and Stefan Wagner

Position

1 PhD position for 3 years with a possibility of extension, 100 %, TV-L E13

What we are looking for:

A successful candidate is expected to have in-depth knowledge in at least one of the areas listed below and interest in the other two areas:

  • Test and diagnosis methods for digital microelectronics, esp. test-access mechanisms.
  • Software test methods, esp. coverage metrics and performance stress test generation.
  • Design of multi-processor systems on chip (MPSoCs).

Applications which do not explicitly mention specific competences or experiences in one of these areas will not be considered.

Abstract:

System-Level Test (SLT), where actual application software is run on the circuit, has emerged as an important additional test method for complex systems-on-chip (SoCs). Modern SoCs are self-aware: they include a “DFX infrastructure” of sensors and monitors that collect data about parameters such as temperature and power consumption. Project P5 focuses on generation of SLT programs with desired characteristics while leveraging self-awareness features. The project’s objectives are:

  • Automated methods to produce SLT programs with extra-functional properties, like power consumption, based on model-driven performance stress test generation from high-level software architecture models.

  • Coverage metrics for SLT, leveraging latest results from the field of integration test.

  • Incorporation of the SoC’s self-awareness into SLT, coordinated and assisted by the automatic test equipment during test application. For example, an SLT program may apply stress tests while monitoring a current sensor,
    stopping once the desired temperature has been reached.

Project lead

Bin Yang

We are looking for

A motivated applicant with a very good master’s degree in electrical engineering and information technology or computer science. The candidate should have a strong background in machine learning, deep learning and high programming skills.

Project summary

This project aims to tackle challenges occurring in post-silicon validation with visual analytics methods. Visual analytics helps users analyze complex problems iteratively and supports the steering of complex analysis processes. It therefore constitutes a valid approach to address some of the difficult problems occurring in post-silicon analysis. These include the comparison of high-dimensional test parameters and output parameter spaces, the sparseness of errors and resulting difficulties to develop hypotheses on problem causes, as well as the validation of hypotheses including the generation of new test parameters if necessary.

Post-silicon validation deals with the test of devices under test (DUT) in order to find and correct design bugs before mass production. For doing this, up to several hundreds of input variables or features are recorded. They characterize the input stimuli to the DUT, various tuning parameters and environmental conditions. At the same time, some target variables are calculated from the responses of the DUT. By studying the relationship between the input and target variables, design bugs and unexpected effects have to be detected, localized and mitigated. The goal of this project is to develop efficient methods for input variable selection to simplify post-silicon validation, with a focus on new deep learning based approaches.

The research in this project is planned to lead to a doctoral thesis in electrical engineering and information technology (Dr.-Ing.). To support successful research for the thesis, we provide an excellent research environment with the Graduate School “Intelligent Methods for Semiconductor Test and Reliability” (GS-IMTR), the cooperation with ADVANTEST, as well as with the Institute of Signal Processing and System Theory (ISS) at the University of Stuttgart.

Project lead

Ingmar Kallfass

We are looking for
  • MSc graduate in electrical engineering and information technology or a related field
  • Experience in microwave circuit design in RF-CMOS, SiGe HBT and/or III-V compound semiconductor technologies
  • Knowledge of the theory of microwave engineering, linear and non-linear analog circuit design
  • Hands-on experience of CAD simulation environments like Cadence, ADS and/or Microwave Office
  • The wish to integrate and collaborate in a team of fellow microwave engineers

Abstract:
INWAVE addresses the research area “Advanced design methodologies for testing next generation and beyond RF devices” with a miniaturized and multi-functional frequency extension into the high millimeter-wave frequency range for RF testing. The millimeter-wave RF interface module (RFIM) will employ modern high-speed semiconductor technologies to cover the frequency range from 20 to 86 GHz. The project covers the most challenging components of an entire transceiver chain, including RF up-conversion, RF multi-pole switching, RF variable amplification and power amplification, RF filtering and LO multiplication. In a first project phase a “system level study” will be conducted, comprising the identification of suitable technology choices, prospective circuit implementations and system-level simulations to derive specifications of the functional building blocks. The second phase of the project will see the production-ready circuit design, implementation and test of the RFIM in the technologies identified in phase 1.

Project lead

Stefan Wagner, Steffen Becker, André van Hoorn

What we are looking for

A motivated applicant with a very good master's degree in software engineering, computer science or a related field. The candidate should have strong programming skills. A background in software testing is beneficial.

Abstract

This project aims to advance the state-of-the-art in software test suite optimisation for software with high data-volume, supporting unknown third-party code and tightly coupled with hardware by a novel combination of tailored techniques from functional and non-functional software testing as well as innovative optimisation methods. The project covers the domain of software-intensive automated test execution environments for semi-conductors in particular but aims to contribute to systems with similar characteristics in general.

The open positions are integrated into the GS-IMTR which provide

  • A structured, quality-assured and interdisciplinary education programme;
  • Subject-specific lectures and seminars for soft skills and interpersonal skills;
  • International networking during a stay at research institutes abroad.

Applicants should hold a master’s or equivalent degree in electrical engineering, computer science, information technology, mathematics, physics, or a related discipline with above-average results. They are expected to show a high level of proficiency in both spoken and written English.

Please send your application (cover letter, academic CV, letter of motivation indicating your favorite project(s), degree certificates and transcripts of records from Bachelor/Master, names of potential academic referees) either by post to Prof. Dr. Dirk Pflüger, Institute for Parallel and Distributed Systems, Universitätsstr. 38, 70569 Stuttgart, Germany, or electronically in a single PDF file (up to 10 MB) to application@gs-imtr.uni-stuttgart.de to arrive no later than January 28, 2020. Depending on availability, later submissions might be taken into consideration.

The University of Stuttgart is an equal opportunities employer. Applications from women are especially encouraged. Severely challenged persons will be given preference in case of equal professional qualifications.

Contact

Dirk Pflüger
Prof. Dr. rer. nat.

Dirk Pflüger

Institute for Parallel and Distributed Systems (IPVS)

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