Download of Workshop Materials
Workshop speakers were free to provide materials (slides or papers) for publications. The provided materials are available from the list below.
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Paper: Maximizing Power Consumption by Exploiting Genetic Algorithms for Automatic System-Level Test Program Generation, Denis Schwachhofer, Francesco Angione, Steffen Becker, Stefan Wagner, Matthias Sauer, Paolo Bernardi, Ilia Polian
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Program
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Slides: Self-Learning Tuning for Post-Silicon Validation, Peter Domanski
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Slides: Tackling Test and Diagnosis Challenges Using GPU-Base High-Throughput Timing Simulation, Stefan Holst
Workshop on Intelligent Methods for Test and Reliability (IMTR’23)
Workshop Scope
Data collected during different test-related design, manufacturing, and operation steps bear huge potential that is heavily under-utilized today. As a consequence, test methods are undergoing a transformation triggered by the advent of next-generation artificial intelligence and data science technology. This workshop aims at bringing the core test community together with interdisciplinary researchers working on various facets of intelligent methods within the test flow. This workshop will leverage the interdisciplinary potentials to consider intelligent methods for test-related problems from the points of view of both: the ETS community and researchers working in different scientific areas, such as machine learning, data science, security, software engineering, and visualization.
Call for Papers
The workshop invites submissions on, but not limited to, the following topics:
- Intelligent methods, including machine learning, data and visual analytics, for test and reliability problems (design for testability, post-silicon validation, test application, yield optimization, fault-tolerant operation)
- Secure and privacy-preserving semiconductor testing
- Intelligent techniques for system-level test
- Data-driven software engineering for handling test-related data
- Intelligent solutions for ultra-high speed, ultra-high data rate test application
A submission can describe a novel scientific result, provide a position statement about a new and relevant problem, or report a case study on practical experiences with a technique from the list above. The submissions should not be formally published in the past. The workshop will have no formal proceedings, so authors will be free to resubmit their work to conferences or journals. Accepted papers can, at the discretion and with an approval of their authors, be published on the workshop’s website.
Author instructions:
Submissions in form of full 6-page papers or 1-2 page extended abstracts (in IEEE double-column format, either A4 or US Letter) should be submitted through EasyChair:
Key dates:
Extended submission deadline: February 15, 2023 February 28 March 20, 2023
Acceptance notification: April 1, 2023
PDF file for publishing on the workshop’s website (optional): May 10, 2023
Workshop: May 25-26, 2023
Registration:
This workshop is co-located with the IEEE European Test Symposium and will use its registration facilities. Please register through the ETS website:
Technical Program
16:00 Introduction to the Workshop
Dirk Pflueger, Matthias Sauer, Matteo Sonza Reorda, Hussam Amrouch, Krishnendu Chakrabarty, Said Hamdioui, Ilia Polian (U Stuttgart, DE, Advantest Europe, DE, Politecnico di Torino, IT, TU Munich, DE, Duke U, US, TU Delft, NL)
16:10 Invited talk Jennifer Dworak
Why Should DFT Stop at Test? Reusing DFT in Functional Mode
Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore Manikas, and Kundan Nepal
16:40 Panel
Emerging Technologies: Seamless Integration or long Journey of Adaptation?
Organizer: Hussam Amrouch (U Stuttgart, DE and TU Munich, DE)
Panelists: Said Hamdioui (TU Delft), Lilas Alrahis (New York U Abu Dhabi, UAE), Matthias Sauer (Advantest, DE), Abhijit Chatterjee (Georgia Tech, US)
17:40 Technical Papers
QMESy: Towards Quality Measurement for Explanations in System Design
Goerschwin Fey, Swantje Plambeck and Bernhard J. Berger, TU Hamburg-Harburg
Multipars: Reduced-Communication MPC over $\mathbb Z_{2^k}$
Sebastian Hasler, Pascal Reisert, Marc Rivinius and Ralf Küsters, U Stuttgart
Maximizing Power Consumption by Exploiting Genetic Algorithms for Automatic System-Level Test Program Generation
Denis Schwachhofer, Francesco Angione, Steffen Becker, Stefan Wagner, Matthias Sauer, Paolo Bernardi and Ilia Polian, U Stuttgart, Politecnico di Torino, Advantest
18:45 Reception
8:30 Invited Talk Lilas Alrahis
PoisonedGNN: Backdoor Attack on Graph Neural Networks-based Hardware Security Systems
Lilas Alrahis and Ozgur Sinanoglu (New York U Abu Dhabi, UAE)
9:00 Poster Session: Projects of Graduate School Intelligent Methods for Test and Reliability
(including 5-minute pitches)
Visual Analytics for Post-Silicon Validation
Andrés Lalama, Thomas Ertl, Daniel Weiskopf, Steffen Koch (U Stuttgart, DE)
Self-Learning Tuning for Post-Silicon Validation
Peter Domanski, Dirk Pflüger (U Stuttgart, DE)
Hyperdimensional Computing for Chip Testing -Towards Learning Fast from Little Data
Paul Genßler, Hussam Amrouch (U Stuttgart, DE and TU Munich, DE)
Online Evaluation of System Health State
Hanieh Jafarzadeh, Hans-Joachim Wunderlich (U Stuttgart)
Design for Testing and Reliability in the Presence of Transistor Self-Heating for Advanced Technologies
Florian Klemme, Hussam Amrouch (U Stuttgart, DE and TU Munich, DE)
Secure and Privacy-Preserving Semiconductor Testing
Sebastian Hasler, Ralf Küsters (U Stuttgart, DE)
Systematic Analysis of System-Level Test Fails
Nourhan Elhamawy, Jens Anders, Ilia Polian (U Stuttgart, DE)
Automated Generation of System-Level Test Programs for Characterization of Parametric Device Properties
Denis Schwachhofer, Ilia Polian, Stefan Wagner, Steffen Becker (U Stuttgart, DE)
10:00 Coffee Break
10:30 Session 2: Joint session with AI-Treats
12:30 Lunch
13:30 Keynote Yervant Zorian
Title TBD
Yervant Zorian (Synopsys, US)
14:15 Keynote Georges Gielen
Improving defect coverage for analog/mixed-signal ICs: machine learning to the rescue
Georges Gielen (KU Leuven, BE)
15:00 Invited Talk Stefan Holst
Tackling Test and Diagnosis Challenges Using GPU-Based High-Throughput Timing Simulation
Stefan Holst (Kyushu Insititute of Technology, JP)
15:30 Workshop Wrap Up
Workshop organizers:
This workshop is organized by the Graduate School Intelligent Methods for Test and Reliability (GS-IMTR), a joint program between the University of Stuttgart and Advantest.
General Chairs: Dirk Pflueger (University of Stuttgart, Speaker of GS-IMTR), Matthias Sauer (Advantest Europe), Matteo Sonza Reorda (Politecnico di Torino)
Program Chairs: Hussam Amrouch (University of Stuttgart), Krishnendu Chakrabarty (Duke University), Said Hamdioui (TU Delft), Ilia Polian (University of Stuttgart)
Programm Commitee: TBD