Workshop on Intelligent Methods for Test and Reliability (IMTR'25)

16:30 Introduction to the Workshop

Dirk Pflüger, Matthias Sauer, Matteo Sonza Reorda, Hussam Amrouch, Krishnendu Chakrabarty, Said Hamdioui, Ilia Polian (U Stuttgart, DE, Advantest Europe, DE, Politecnico di Torino, IT, TU Munich, DE, Duke U, US, TU Delft, NL)

16:35 Invited talk Jeff Rearick

Test Harder or Test Smarter? 
Jeff Rearick, AMD

17:05 Break

17:15 Session 1 Unconventional Approaches to Test and Reliability

Intelligent Sensing and On-Chip Learning for Silicon Lifecyle Management
Tim Strobel, Sarah Rottacker and Jens Anders, U Stuttgart, Advantest

ARBoard: See Beyond the Circuit
Giorgio Insinga, Reem Khattar, Paolo Bernardi and Pietro Bella, Politecnico di Torino

Comparison of Multiple Methods for System-Level Test Program Generation Targeting Non-functional Properties
Denis Schwachhofer, Steffen Becker, Stefan Wagner, Matthias Sauer and Ilia Polian, U Stuttgart, TU Munich, Advantest

18:15 Invited talk Leticia Bolzani Poehls

Lifecycle Management Strategy for Addressing Heterogeneous Integration Challenges in AI-Architectures
Leticia Bolzani Poehls, IHP - Leibniz Institute for High Performance Microelectronics, Germany

18:45 Reception

8:30 Invited talk Daniel Müller-Gritschneder

Low Overhead Fault Tolerance for tinyML and Security Applications 
Daniel Müller-Gritschneder, TU Vienna, Austria

9:00 Session 2: Artificial Intelligence Techniques for Testing

Graph Attention Networks to Identify the Impact of Transistor Degradation on Circuit Reliability 
Tarek Mohamed, Victor van Santen, Lilas Alrahis, Ozgur Sinanoglu and Hussam Amrouch, U Stuttgart, TU Munich, New York U Abu Dhabi

A Hitchhiker's Guide to LLM Fine-Tuning for Semiconductor Testing
Linus Bantel, Sarah Rottacker and Dirk Pflüger and U Stuttgart, Advantest

A Symbolic Regression Based Variable Selection Method for Automated Feature Design
Yang Yang, Yiwen Liao and Bin Yang, U Stuttgart, Advantest

10:00 Coffee Break

10:30 Invited Talk Jürgen Alt

Design and Test – Who sets the direction? 
Jürgen Alt, Infineon

11:00 Session 3: Test Quality and Security

Machine Learning Based Detection of Marginal Defects in Standard Cells
Karthik Pandaram, Hussam Amrouch and Ilia Polian, U Stuttgart, TU Munich

Influence of Automated Test Equipment Drift on Process Capability Studies
Anand Venkatachalam, Ernst Aderholz, Matthias Sauer, Simon Schweizer, Matthias Werner and Ilia Polian, U Stuttgart, Infineon, Advantest

Non-Interactive Preprocessing for Multi-Party Computation
Sebastian Hasler, Pascal Reisert and Ralf Küsters, U Stuttgart

12:00 Invited Talk Paolo Bernardi

Advances in System-Level Test
Paolo Bernardi, Politecnico di Torino

12:30 Lunch

13:30 Session 4: Modeling and Simulation

Parameterized Virtual Testing and Simulation of Verilog-AMS Behavioral Models
Thorben Schey, Khaled Karoonlatifi, Michael Weyrich and Andrey Morozov, U Stuttgart, Advantest

Using the KyuPy Simulator for System-Level Test
Nourhan Elhamawy, Jens Anders, Ilia Polian and Matthias Sauer, U Stuttgart, Advantest

Modeling the Impact of Magnetic Field on FDSOI and FinFET
Munazza Sayed and Hussam Amrouch, U Stuttgart, TU Munich

14:30 Invited Talk Tsun-Ming Tseng

Design Automation for Wavelength-Routed Optical Networks-on-Chip: Current Solutions and Reliability Challenges
Tsun-Ming Tseng, Technical University of Munich

15:00 Workshop Wrap Up

Test Harder or Test Smarter? 
Jeff Rearick, AMD

The advent of the Mega Data Center gave rise to a unique opportunity: studying how millions of supposedly identical circuits (CPU or GPU cores) hold up in the field under high-use conditions. Initial results published by the hyperscalers indicate that there is room for improvement. This talk explores several methods for testing such devices with the goal of ensuring a lifetime of reliable operation, spanning time zero testing in the factory to online testing in situ.
These pros and cons of these methods are examined to identify areas where more thorough testing could be applied (“test harder”), as well as others where perhaps more intelligent testing would add value (“test smarter”). This analysis points out that there are implications for many steps in the process of outfitting a data center, from specifying the Design For Testability methodology of the chips, to the feature sets of the test equipment used in manufacturing, to the periodic maintenance policies in the data center, and even with the relationship between the customer and the supplier.
These lessons, though based on observations in a high-volume / high-stress environment, seem to be applicable to many other market segments in our industry. The talk concludes with some speculation about common approaches that may be worthy of wide deployment to improve quality while managing cost.

Bio: Jeff Rearick has over 40 years of experience in the test field. The first half of his career was spent at Hewlett-Packard (and the spin-off to Agilent Technologies), the latter half at Advanced Micro Devices, with the common theme of Design For Testability throughout. Jeff serves on the Steering Committee of the International Test Conference (where he was Program Chair in 2023), is busily working as the Editor for draft standards in three related IEEE Working Groups (1687, P1687.1, P1687.2), and holds 50 patents. He has degrees from Purdue University and the University of Illinois.

Lifecycle Management Strategy for Addressing Heterogeneous Integration Challenges in AI-Architectures
Leticia Bolzani Poehls, IHP - Leibniz Institute for High Performance Microelectronics, Germany

The always increasing integration level of very complex CMOS- and emerging technology-based circuits in heterogenous architectures requires a holistic approach to properly address all quality and reliability issues. In more detail, state-of-the-art architectures developed for implementing high performance applications are being implemented using not only CMOS technology, but also emerging technologies, such as memristive devices. Memristive devices can assume at least two different resistive states, being able to implement not only memory elements, but also computing elements. Different types of memristive devices, classified according to their switching mode, conductive path and working mechanism. In this context, Resistive Random-Access Memories (RRAMs) represent one of the most promising candidates to complement and/or replace CMOS technology. These emerging memories address issues related to traditional memories’ manufacturing process, reliability, power consumption and performance. Despite these advantages, RRAMs are also susceptible to manufacturing deviations affecting their quality at time zero as well as to time-dependent deviations, which compromise their reliability during lifetime. In addition, the integration of these emerging memories with CMOS-based circuits poses significant design challenges. Thus, a holistic approach able to properly address these challenges, from design to obsolescence, is considered mandatory. Thus, the goal of this talk is to present the idea behind the lifecycle management approach assuming CMOS- and emerging technology-based architecture heterogeneous integration. A discussion about the main sources of quality and reliability issues according to the lifecycle phases as well as the possible solutions able to address these main issues will be presented. Finally, this talk will allow attendees to understand the lifecycle management choices available to ensure high-quality and -reliable state-of-the-art architectures based on CMOS and emerging technologies.

Bio: Leticia Maria Bolzani Pöhls graduated in Computer Science at UFPel (Brazil) in 2002 and holds a master’s degree in Electrical Engineering from PUCRS (Brazil) since 2004. In 2008 she obtained her Ph.D. in Computer Engineering from Politecnico di Torino (Italy). From 2010 to 2022 she was Professor at the School of Technology at PUCRS (Brazil). For her sabbatical year she joined the Chair of Integrated Digital Circuits and System Design (IDS) at RWTH Aachen University (Germany) in 2019. In 2020 she created and until 2024 led the Group of Test and Reliability of Emerging Applications at IDS. In January 2025 she joined IHP - Leibniz Institute for High Performance Microelectronics (Germany) where she is leading the Group of Neuromorphic Hardware in the Department of System Architectures. Amongst her activities in the scientific community, she works as a member of the Steering Committee of IEEE Latin American Test Symposium (LATS) as well as the working group of VLSI-SoC. In addition, she is part of the organizing committee of several conferences such as ETS, DATE, DDECS, VTS, and ITC. Finally, she received the 2021 JETTA-TTTC Best Paper Award, the IEEE LATS2022 Best Paper Award, and the HiPEAC 2023 Paper Award for her paper at the Design Automation Conference (DAC2023).

Low Overhead Fault Tolerance for tinyML and Security Applications 
Daniel Müller-Gritschneder, TU Vienna, Austria

Random HW faults as well as targeted fault attacks jeopardize the safety and security of digital systems respectively. The standard protection approach relies on the insertion of spatial HW or temporal SW redundancy to detect errors before they propagate to critical parts of the system and create safety or security hazards. Redundancy comes at high costs, usually more than 2X for dual-modular and more than 3X for triple modular redundancy. To reduce these costs, selective hardening or specialized protection scheme such as algorithmic based fault tolerance (ABFT) can be applied. In this talk, we cover several systematic approaches to apply selective hardening and ABFT for tinyML and security applications. In order to evaluate these schemes a fast open source fault injection environment based on Verilator is presented.

Bio: Daniel Müller-Gritschneder is a full professor for Computer Architecture at the Institute of Computer Engineering, Informatics, TU Wien. He received his Diploma, doctoral and habilitation degree in electrical engineering and information technology from TU Munich in 2003,2009 and 2019 respectively, where he was also a researcher at the Chair of Electronic Design Automation between 2004 and 2024. He worked on several projects in close cooperation with industry partners such as Infineon, Intel, Siemens and Bosch. He serves as TPC member at EDA conferences such as DAC, ICCAD, SAMOS and CODES/ISSS and was co-organizer of the RISC-V Summit Europe 23 and 24. He is a senior member of IEEE. His main interests are in Electronic System Level Design, RISC-V, tinyML as well as functional safety and HW security.

Design and Test – Who sets the direction? 
Jürgen Alt, Infineon

Testing during the manufacturing process is a crucial cost component for all semiconductor products. The discipline of Design-for-Test (DfT) plays an essential role in influencing both the expenses to test every device and the efforts to prepare for test. This presentation focuses on System-on-Chip (SoC) designs to explore the balance between test efforts and design efforts, ultimately aiming for optimal cost efficiency.

Bio: Juergen Alt is Senior Principal Engineer at Infineon. Within Infineon’s architecture group for Automotive Microcontrollers, he is responsible for test concept and Design-for-Test architecture of next generation microcontroller platform. He is in business for 25+ years working on Design & Test, Electronic Design Automation and reliability topics for Intel and Infineon. He contributed to various university and industry collaboration projects. At Friedrich-Alexander University Erlangen, Germany he is lecturer for DfT courses, and he contributed to multiple conferences by regular presentations. Juergen is based in Munich, Germany and has diploma and doctoral degrees in electrical engineering both from University of Hannover, Germany.

Advances in System-Level Test
Paolo Bernardi, Politecnico di Torino

Since the inception of IC design in the mid-1960s, IC test has been an integral part of the manufacturing process. Initially, tests were of a Functional nature of either randomly generated or created from verification suites. But as chips got larger, testing required a more targeted approach, one that needed to be easily replicated from one design to another. This led to the invention of Structural methods like scan, which made designs combinational and simplified the test generation process. After almost 50 years, the testing scenario has evolved just slightly, following technology trends currently led by the complexity of the circuits under test and the field of use (i.e., Automotive). Structural methods are still dominant, at least during the manufacturing test process, but Functional techniques are now recognized to be useful to complement structural techniques during the manufacturing test process, such as System-Level-Test.

The talk discusses some today-relevant System-Level-Test (SLT) techniques. Automotive chip case studies from STMicroelectronics will be illustrated.

Bio:Paolo Bernardi (MS'02 and PhD'06 in Computer Science) is an Associate Professor of the Politecnico di Torino University, working in the Electronic CAD and Reliability research group. His current interests include System-on-Chip test and reliability, especially in the direction of high-quality automotive devices. Prof. Bernardi has been the General Chair of the European Test Symposium 2023 (ETS23) and is the current Program Chair of the International Test Conference (ITC25). He is an IEEE senior member.

Design Automation for Wavelength-Routed Optical Networks-on-Chip: Current Solutions and Reliability Challenges
Tsun-Ming Tseng, Technical University of Munich

Enabled by wavelength-division multiplexing, photonic interconnected integrated systems are considered a promising option to support high-bandwidth communications for AI/ML and HPC applications. Among different types of photonic interconnects, wavelength-routed optical networks-on-chip (WRONoC) is renowned for supporting collision-free simultaneous data transmission among all network nodes without arbitration. This talk will cover both topological and physical design of WRONoCs, featuring bit-level parallelism and reliability challenges brought by crosstalk and process variation. Some potential research directions of WRONoCs will be discussed at the end of this talk.

Bio:Tsun-Ming Tseng received the Dr.-Ing. degree from Technical University of Munich (TUM) in 2017. He leads a research group in the Chair of Electronic Design Automation (EDA) at TUM. His research interests focus on design automation for emerging technologies, including microfluidic biochips, optical networks-on-chip, and novel microfabrication. He also works on traditional EDA problems. He serves in the TPC of ASP-DAC and ISPD, and in the Blue Ribbon Panel of NSF - LEAP HI. His research has been funded by DFG, BMBF, and Bavarian Chip-Design-Centre (BCDC).