Abstract: Graph Neural Networks (GNNs) successfully facilitate learning on graph-structured data, such as social networks, recommendation systems, and protein-protein interactions. Since electronic circuits can be represented naturally as graphs, GNNs provide great potential to advance Machine Learning (ML)-based methods for all aspects of electronic system design and Computer-Aided Design (CAD). This talk provides an overview of how GNNs get designed and employed to learn the properties of circuits. Taking hardware security and circuit reliability assessments as target applications, this talk first illustrates how GNNs aid in analyzing flattened/unstructured gate-level netlists, then demonstrates how to employ GNNs to accurately estimate the impact of process variations and device aging on the delay of any path within a circuit.
Bio: Lilas Alrahis received the M.Sc. degree and the Ph.D. degree in Electrical and Computer Engineering from Khalifa University, UAE, in 2016 and 2021, respectively. She is currently a Postdoctoral Associate with the Design for Excellence Lab, headed by Prof. Ozgur Sinanoglu, in the Division of Engineering, at the New York University Abu Dhabi (NYUAD), UAE. Her current research interests include Hardware Security, Design-for-Trust, Logic Locking, Applied Machine Learning, and Digital Logic Design. Dr. Alrahis is currently serving as Associate Editor of the Integration, the VLSI Journal. She is also a frequent reviewer for top journals including IEEE Transactions on Information Forensics and Security, IEEE Access, and IEEE Embedded Systems Letters. She was a program committee member of the Euromicro Conference on Digital System Design (DSD2021 and DSD2022). Dr. Alrahis won the MWSCAS Myril B. Reed Best Paper Award in 2016 and the Best Paper Award at the Applied Research Competition held in conjunction with Cyber Security Awareness Week in 2019 and 2021.
